/*
 @file drv_ftm.c

 @date 2011-11-16

 @version v2.0

 This file provides all sys alloc function
*/

#if defined(ARCTIC)
#include "sal.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_ftm.h"
#include "usw/include/drv_common.h"
#include "usw/include/drv_sdb.h"
#include "drv_api.h"

#define DRV_FTM_NSH_MODE_NONE           0b000
#define DRV_FTM_NSH_MODE_ESCL0          0b100
#define DRV_FTM_NSH_MODE_ESCL1          0b101
#define DRV_FTM_NSH_MODE_ESCL0_PART     0b110
#define DRV_FTM_NSH_MODE_ESCL1_PART     0b111

#define DRV_BITS_NUM_OF_WORD                32          /**< Bits num of word */
#define DRV_FTM_REALLOC_TCAM 1

#define DYNAMIC_SLICE0_ADDR_BASE_OFFSET_TO_DUP 0x60000000
#define DYNAMIC_SLICE1_ADDR_BASE_OFFSET_TO_DUP 0x40000000

#define DRV_FTM_TBL_INFO(sram_type)   g_at_ftm_master[lchip]->p_sram_tbl_info[sram_type]
#define DRV_FTM_KEY_INFO(sram_type)   g_at_ftm_master[lchip]->p_tcam_key_info[sram_type]
#define DRV_FTM_SRAM_DB(mem_id)    g_at_ftm_master[lchip]->sram_db[mem_id]

#define DRV_FTM_TBL_ACCESS_FLAG(sram_type)               DRV_FTM_TBL_INFO(sram_type).access_flag
#define DRV_FTM_TBL_MAX_ENTRY_NUM(sram_type)             DRV_FTM_TBL_INFO(sram_type).max_entry_num
#define DRV_FTM_TBL_MEM_BITMAP(sram_type)                DRV_FTM_TBL_INFO(sram_type).mem_bitmap
#define DRV_FTM_TBL_COUPLE_MODE(sram_type)               DRV_FTM_TBL_INFO(sram_type).couple_mode

#define DRV_FTM_TBL_MEM_START_OFFSET(tbl_id, mem_id)  DRV_FTM_SRAM_DB(mem_id).mem_offset
#define DRV_FTM_TBL_MEM_ENTRY_NUM(tbl_id, mem_id)     DRV_FTM_SRAM_DB(mem_id).entry_num
#define DRV_FTM_TBL_HASH_POLY(tbl_id)                 DRV_FTM_TBL_INFO(tbl_id).hash_poly

#define DRV_FTM_TBL_BASE_BITMAP(tbl_id)               DRV_FTM_TBL_INFO(tbl_id).connect_bitmap
#define DRV_FTM_TBL_BASE_MIN(tbl_id, i)               (_drv_at_ftm_get_sram_db_node(lchip, tbl_id, i))->min_index
#define DRV_FTM_TBL_BASE_MAX(tbl_id, i)               (_drv_at_ftm_get_sram_db_node(lchip, tbl_id, i))->max_index

#define DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id)             DRV_MEM_ENTRY_NUM(lchip, mem_id)
#define DRV_FTM_MEM_HW_DATA_BASE(mem_id)              DRV_MEM_ADD3W(lchip, mem_id)
#define DRV_FTM_MEM_HW_DATA_BASE6W(mem_id)            DRV_MEM_ADD6W(lchip, mem_id)
#define DRV_FTM_MEM_HW_DATA_BASE12W(mem_id)           DRV_MEM_ADD12W(lchip, mem_id)
#define DRV_FTM_MEM_HW_MASK_BASE(mem_id)              DRV_MEM_ADD6W(lchip, mem_id)
#define DRV_FTM_MEM_HW_GEMPORT_BASE(mem_id)           DRV_MEM_ADD3W(lchip, mem_id)
#define DRV_FTM_MEM_HW_MPLS_BASE(mem_id)              DRV_MEM_ADD6W(lchip, mem_id)

#define DRV_FTM_KEY_MAX_INDEX(tbl_id)                  DRV_FTM_KEY_INFO(tbl_id).max_key_index
#define DRV_FTM_KEY_MEM_BITMAP(tbl_id)                 DRV_FTM_KEY_INFO(tbl_id).mem_bitmap
#define DRV_FTM_KEY_ENTRY_NUM(tbl_id, type, mem_id)    DRV_FTM_KEY_INFO(tbl_id).entry_num[type][mem_id]
#define DRV_FTM_KEY_START_OFFSET(tbl_id, type, mem_id) DRV_FTM_KEY_INFO(tbl_id).start_offset[type][mem_id]

#define DRV_FTM_POLY_TYPE_MAX 16

#define DRV_FTM_ADD_TABLE(mem_id, table, start, size) \
    do { \
        if (size!=0) \
        { \
            DRV_BMP_SET(DRV_FTM_TBL_MEM_BITMAP(table), mem_id); \
            DRV_FTM_SRAM_DB(mem_id).block_id = DRV_FTM_TBL_INFO(table).sram_num;\
            DRV_FTM_TBL_INFO(table).sram_id_a[DRV_FTM_TBL_INFO(table).sram_num++] = mem_id;\
            DRV_FTM_TBL_MAX_ENTRY_NUM(table)            += size; \
            DRV_FTM_TBL_MEM_START_OFFSET(table, mem_id) = start; \
            DRV_FTM_TBL_MEM_ENTRY_NUM(table, mem_id)    = size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
        } \
    } while (0)

#define DRV_FTM_INIT_MEM_PART(mem_id, num_parts)   \
    do{\
        DRV_FTM_SRAM_DB(mem_id).part = mem_malloc(MEM_FTM_MODULE,num_parts*sizeof(drv_ftm_sram_id_info_t));\
        if (!DRV_FTM_SRAM_DB(mem_id).part)  {return DRV_E_NO_MEMORY;}\
        sal_memset(DRV_FTM_SRAM_DB(mem_id).part, 0, num_parts*sizeof(drv_ftm_sram_id_info_t));\
        DRV_FTM_SRAM_DB(mem_id).part_num = num_parts;\
    }while(0)

#define DRV_FTM_INIT_TABLE_PART(table, mem_num) \
    do{\
        DRV_FTM_TBL_INFO(table).sram_part_a = mem_malloc(MEM_FTM_MODULE,mem_num);\
        if (!DRV_FTM_TBL_INFO(table).sram_part_a)  {return DRV_E_NO_MEMORY;}\
    }while(0)

#define DRV_FTM_ADD_TABLE_PART(mem_id, table, part_id, start, size) \
    do { \
        if (size>0) \
        { \
            DRV_BMP_SET(DRV_FTM_TBL_MEM_BITMAP(table), mem_id); \
            DRV_FTM_SRAM_DB(mem_id).block_id = DRV_FTM_TBL_INFO(table).sram_num;\
            DRV_FTM_TBL_INFO(table).sram_id_a[DRV_FTM_TBL_INFO(table).sram_num] = mem_id;\
            DRV_FTM_TBL_INFO(table).sram_part_a[DRV_FTM_TBL_INFO(table).sram_num++] = part_id;\
            DRV_FTM_TBL_MAX_ENTRY_NUM(table)            += size; \
            DRV_FTM_SRAM_DB(mem_id).part[part_id].mem_offset = start; \
            DRV_FTM_SRAM_DB(mem_id).part[part_id].entry_num  = size; \
            DRV_FTM_SRAM_DB(mem_id).part[part_id].tbl_id  = table; \
            DRV_FTM_SRAM_DB(mem_id).mem_offset = (DRV_FTM_SRAM_DB(mem_id).mem_offset > start) ? start : DRV_FTM_SRAM_DB(mem_id).mem_offset;\
            DRV_FTM_SRAM_DB(mem_id).entry_num += size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
        } \
    } while (0)

#ifdef EMULATION_ENV
#define DRV_FTM_ADD_KEY(mem_id, table, start, size) \
    do { \
            DRV_BMP_SET(DRV_FTM_KEY_MEM_BITMAP(table), (mem_id-DRV_FTM_TCAM_KEY0)); \
            DRV_FTM_KEY_MAX_INDEX(table)                += size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
    } while (0)

#define DRV_FTM_ADD_LPM_KEY(mem_id, table, start, size) \
    do { \
            DRV_BMP_SET(DRV_FTM_KEY_MEM_BITMAP(table), (mem_id-DRV_FTM_LPM_TCAM_KEY0)); \
            DRV_FTM_KEY_MAX_INDEX(table)                += size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
    } while (0)
#else
#define DRV_FTM_ADD_KEY(mem_id, table, start, size) \
    do { \
        if (size!=0) \
        { \
            DRV_BMP_SET(DRV_FTM_KEY_MEM_BITMAP(table), (mem_id-DRV_FTM_TCAM_KEY0)); \
            DRV_FTM_KEY_MAX_INDEX(table)                += size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id+DRV_FTM_TCAM_AD0-DRV_FTM_TCAM_KEY0);\
        } \
    } while (0)

#define DRV_FTM_ADD_LPM_KEY(mem_id, table, start, size) \
    do { \
        if (size!=0) \
        { \
            DRV_BMP_SET(DRV_FTM_KEY_MEM_BITMAP(table), (mem_id-DRV_FTM_LPM_TCAM_KEY0)); \
            DRV_FTM_KEY_MAX_INDEX(table)                += size; \
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
            DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id+DRV_FTM_LPM_TCAM_AD0-DRV_FTM_LPM_TCAM_KEY0);\
        } \
    } while (0)
#endif
#define DRV_FTM_ADD_KEY_BYTYPE(mem_id, table, type, start, size) \
    do { \
        if (size!=0) \
        { \
           DRV_FTM_KEY_START_OFFSET(table, type, mem_id - DRV_FTM_TCAM_KEY0)       = start; \
           DRV_FTM_KEY_ENTRY_NUM(table, type, mem_id - DRV_FTM_TCAM_KEY0)          = size; \
        } \
    } while (0)

#define DRV_FTM_ADD_LPM_KEY_BYTYPE(mem_id, table, type, start, size) \
    do { \
        if (size!=0) \
        { \
           DRV_FTM_KEY_START_OFFSET(table, type, mem_id - DRV_FTM_LPM_TCAM_KEY0)       = start; \
           DRV_FTM_KEY_ENTRY_NUM(table, type, mem_id - DRV_FTM_LPM_TCAM_KEY0)          = size; \
           DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id);\
           DRV_BMP_SET(g_at_ftm_master[lchip]->mem_used, mem_id+DRV_FTM_LPM_TCAM_AD0-DRV_FTM_LPM_TCAM_KEY0);\
        } \
    } while (0)


#define DRV_FTM_ADD_FULL_TABLE(mem_id, table, couple) \
        do {\
            uint8 multi = (table == DRV_FTM_SRAM_TBL_MPLS_HASH_KEY) ? 2 : 1; \
            if (couple != 0) \
            {\
                DRV_FTM_ADD_TABLE(mem_id, table, 0, (DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id)*2*multi));\
                DRV_FTM_TBL_COUPLE_MODE(table) = 1;\
            } else {\
                DRV_FTM_ADD_TABLE(mem_id, table, 0, DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id)*multi);    \
            }\
        } while (0)

#define DRV_FTM_ADD_FULL_KEY(mem_id, table) \
        do { \
            uint32 entry_num = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id);\
            DRV_FTM_ADD_KEY(mem_id, table, 0, entry_num);\
       } while (0)

/* single/double 2 chose 1 */
#define DRV_FTM_ADD_LPM_FULL_KEY(mem_id, table)                                                             \
    do {                                                                                                \
        uint32 entry_num = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id);                                           \
        DRV_FTM_ADD_LPM_KEY(mem_id, table, 0, entry_num);                                               \
     } while (0)

enum drv_ftm_dyn_cam_type_e
{
    DRV_FTM_DYN_AD_DS_FLOW,
    DRV_FTM_DYN_AD_DS_IP,
    DRV_FTM_DYN_AD_DS_MAC,
    DRV_FTM_DYN_AD_DS_MPLS,
    DRV_FTM_DYN_AD_DS_SCL0,
    DRV_FTM_DYN_AD_DS_SCL1,
    DRV_FTM_DYN_EDIT_DS_FWD_POST,
    DRV_FTM_DYN_EDIT_DSFWD_PRE,
    DRV_FTM_DYN_EDIT_DS_INNER_EDIT,
    DRV_FTM_DYN_EDIT_DS_NEXT_HOP,
    DRV_FTM_DYN_EDIT_DS_NEXT_HOP_MAP,
    DRV_FTM_DYN_EDIT_DS_OUTER_EDIT,
    DRV_FTM_DYN_EDIT_DS_X_EDIT,
    DRV_FTM_DYN_KEY_CPU_ANT_FLOW,
    DRV_FTM_DYN_KEY_DS_AGING_ANT_FLOW,
    DRV_FTM_DYN_KEY_IPE_ANT_FLOW,
    DRV_FTM_DYN_KEY_LINK_AGG_ANT_FLOW,
    DRV_FTM_DYN_KEY_MAC_KEY,
    DRV_FTM_DYN_KEY_SHARE_MET,

    DRV_FTM_DYN_CAM_TYPE_MAX
};
typedef enum drv_ftm_dyn_cam_type_e drv_ftm_dyn_cam_type_t;

#define DRV_FTM_UNIT_1K 10
#define DRV_FTM_UNIT_8K 13
#define DRV_FTM_FLD_INVALID 0xFFFFFFFF

#define DRV_FTM_MAX_MEM_NUM 8

struct drv_ftm_dyn_ds_base_s
{
    uint32 ds_dynamic_base[16];
    uint32 ds_dynamic_max_index[16];
    uint32 ds_dynamic_min_index[16];
};
typedef struct drv_ftm_dyn_ds_base_s drv_ftm_dyn_ds_base_t;

struct drv_ftm_poly_map_s
{
	uint16 ctc_poly;
	uint16 drv_poly;
};
typedef struct drv_ftm_poly_map_s drv_ftm_poly_map_t;

struct drv_ftm_tbl_poly_s
{
	uint32 sram_id;
	drv_ftm_poly_map_t poly_map[2];	/*0-normal, 1-couple*/
};
typedef struct drv_ftm_tbl_poly_s drv_ftm_tbl_poly_t;

struct drv_ftm_hash_poly_s
{
	drv_ftm_tbl_poly_t* sram_poly;
	uint8 sram_num;
};
typedef struct drv_ftm_hash_poly_s drv_ftm_hash_poly_t;

struct drv_ftm_sram_tbl_info_s
{
    uint32 access_flag; /*judge weather tbl share alloc*/
    uint32 mem_bitmap[DRV_FTM_EDRAM_MAX/DRV_BITS_NUM_OF_WORD+1];
    uint32 max_entry_num;
    drv_ftm_dyn_ds_base_t dyn_ds_base;
    uint32 connect_bitmap;
    uint8  couple_mode;
    uint8  sram_num;
    uint8  rsv[2];
    uint16  sram_id_a[DRV_FTM_MAX_MEM_NUM];
    uint8*  sram_part_a;
    drv_ftm_hash_poly_t hash_poly;
};
typedef struct drv_ftm_sram_tbl_info_s drv_ftm_sram_tbl_info_t;

#define BYTE_TO_4W  12

#define DRV_FTM_TCAM_SIZE_ipv4_pbr 0
#define DRV_FTM_TCAM_SIZE_ipv6_pbr 1
#define DRV_FTM_TCAM_SIZE_ipv4_nat 2
#define DRV_FTM_TCAM_SIZE_ipv6_nat 3

#define DRV_FTM_TCAM_SIZE_halfkey   0
#define DRV_FTM_TCAM_SIZE_singlekey 1
#define DRV_FTM_TCAM_SIZE_doublekey 2

#define DRV_FTM_TCAM_SIZE_LPMhalf   0
#define DRV_FTM_TCAM_SIZE_LPMSingle 1
#define DRV_FTM_TCAM_SIZE_LPMDouble 2

#define DRV_FTM_TCAM_SIZE_MAX 4

#define DRV_FTM_CAM_CHECK_TBL_VALID(cam_type, tbl_id)\
    if ((DRV_FTM_CAM_TYPE_FIB_HOST1_NAT == cam_type)\
        && (DsFibHost1Ipv4NatDaPortHashKey_t != tbl_id))\
    {\
        return DRV_E_HASH_CONFLICT;\
    }

struct drv_ftm_tcam_key_info_s
{
    uint32 mem_bitmap[DRV_FTM_TCAM_TYPE_MAX/DRV_BITS_NUM_OF_WORD+1];
    uint32 max_key_index;
};
typedef struct drv_ftm_tcam_key_info_s drv_ftm_tcam_key_info_t;

typedef struct drv_ftm_sram_id_info_s drv_ftm_sram_id_info_t;
struct drv_ftm_sram_id_info_s
{
    uint32 mem_offset;
    uint32 entry_num;
    uint32 hw_addr;
    uint32 min_index;    /*min index in sram table*/
    uint32 max_index;    /*max index in sram table*/
    uint16 tbl_id;       /*sram table type*/
    uint16 connect_id:6;
    uint16 block_id:6;
    uint16 part_num:4;
    drv_ftm_sram_id_info_t* part;
};

typedef struct g_ftm_master_s g_ftm_master_t;


struct g_ftm_master_s
{
    drv_ftm_sram_tbl_info_t* p_sram_tbl_info;
    drv_ftm_tcam_key_info_t* p_tcam_key_info;

    drv_ftm_sram_id_info_t sram_db[DRV_FTM_EDRAM_MAX];

    uint16  int_tcam_used_entry;
    /*cam*/
    uint8 cfg_max_cam_num[DRV_FTM_CAM_TYPE_MAX];
    uint8 conflict_cam_num[DRV_FTM_CAM_TYPE_MAX];

    /*cam bitmap*/
    uint32 fib1_cam_bitmap0[1];     /*single*/
    uint32 fib1_cam_bitmap1[1];     /*dual*/
    uint32 fib1_cam_bitmap2[1];     /*quad*/

    uint32 userid_cam_bitmap0[1];   /*single*/
    uint32 userid_cam_bitmap1[1];   /*dual*/
    uint32 userid_cam_bitmap2[1];   /*quad*/

    uint32 xcoam_cam_bitmap0[4];    /*single*/
    uint32 xcoam_cam_bitmap1[4];    /*dual*/
    uint32 xcoam_cam_bitmap2[4];    /*quad*/

    uint32 cam_bitmap;
    uint32 host1_poly_type;

    uint32  couple_mode:1;
    uint32  lpm_model:4;
    uint32  nat_pbr_enable:1;
    uint32  napt_enable:1;
    uint32  mpls_enable:1;
    uint32  scl_mode:2;
    uint32  nsh_mode:3;     /* refer to DRV_FTM_NSH_MODE_XXX */
    uint32  rsv:19;

    uint16 tcam_specs[DRV_FTM_TCAM_TYPE_MAX][4];
    uint16 tcam_offset[DRV_FTM_TCAM_TYPE_MAX][4];
    uint32 lpm_tcam_init_bmp[2][3];  //0 private, 1 public; 0: ipv6 full, 1: ipv6 half, 2: ipv4 boundary
    uint32 mem_used[(DRV_FTM_MAX_ID+31)/32];
};

g_ftm_master_t* g_at_ftm_master[30] = {NULL};

#define DRV_BIT_SET(flag, bit)      ((flag) = (flag) | (1 << (bit)))


static uint32 parser_tbl_id_list[] =
{
    DsParserIntTcpCamResultCtl_t,
    DsParserIntUdpCamResultCtl_t,
    DsParserLayer2Decoder_t,
    DsParserLayer3Decoder_t,
    DsParserLayer4Decoder_t,
    ParserDebugStats_t,
    ParserEthernetCtl_t,
    ParserInitDone_t,
    ParserInit_t,
    ParserIpChecksumCtl_t,
    ParserIpCtl_t,
    ParserL3Ctl_t,
    ParserLayer2ProtocolCamValid_t,
    ParserLayer2ProtocolCam_t,
    ParserLayer3ProtocolCamValid_t,
    ParserLayer3ProtocolCam_t,
    ParserLayer3ProtocolCtl_t,
    ParserLayer4AchCtl_t,
    ParserLayer4AppCtl_t,
    ParserLayer4ExtCam_t,
    ParserLayer4FlexCtl_t,
    ParserMplsCtl_t,
    ParserPacketTypeMap_t,
    ParserRangeOpCtl_t,
    ParserReserved_t,
    ParserTrillCtl_t,
    DsL2Decoder_t,
    DsL3Decoder_t,
    DsL4Decoder_t,
    ParserPtpCtl_t
};

static drv_ftm_sram_id_info_t*
_drv_at_ftm_get_sram_db_node(uint8 lchip, uint16 sram_type, uint8 connect_id)
{
    drv_ftm_sram_id_info_t* p_sram_node = NULL;
    uint16 sram_idx = 0;
    uint16 mem_id = 0;
    uint8 part_id = 0;
    do {
        mem_id = DRV_FTM_TBL_INFO(sram_type).sram_id_a[sram_idx];
        if (DRV_FTM_SRAM_DB(mem_id).connect_id == connect_id)
        {
            part_id = DRV_FTM_TBL_INFO(sram_type).sram_part_a ? DRV_FTM_TBL_INFO(sram_type).sram_part_a[sram_idx] : 0;
            break;
        }
    }while(++sram_idx<DRV_FTM_TBL_INFO(sram_type).sram_num);
    p_sram_node = DRV_FTM_TBL_INFO(sram_type).sram_part_a ? (&DRV_FTM_SRAM_DB(mem_id).part[part_id]) : (&DRV_FTM_SRAM_DB(mem_id));
    return p_sram_node;
}

static int32
_drv_at_get_dynamic_ram_couple_mode(uint8 lchip, uint16 sram_type, uint32* couple_mode)
{
    *couple_mode = g_at_ftm_master[lchip]->couple_mode | DRV_FTM_TBL_COUPLE_MODE(sram_type);

    return DRV_E_NONE;
}

static int32
_drv_at_set_dynamic_ram_couple_mode(uint8 lchip, uint32 couple_mode)
{
    g_at_ftm_master[lchip]->couple_mode = couple_mode;
    return DRV_E_NONE;
}

static int32
__drv_at_ftm_get_edram_bitmap(uint8 lchip,
                                     uint8 sram_type,
                                     uint32* bit)
{
    switch (sram_type)
    {
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY0:
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY1:
            bit[DRV_FTM_SRAM2] = 0;
            bit[DRV_FTM_SRAM3] = 1;
            bit[DRV_FTM_SRAM4] = 2;
            bit[DRV_FTM_SRAM5] = 3;
            bit[DRV_FTM_SRAM6] = 4;
            bit[DRV_FTM_SRAM7] = 5;
            break;

        case DRV_FTM_SRAM_TBL_MAC_HASH_KEY:
            bit[DRV_FTM_SRAM0] = 0;
            bit[DRV_FTM_SRAM1] = 1;
            bit[DRV_FTM_SRAM2] = 2;
            bit[DRV_FTM_SRAM3] = 3;
            bit[DRV_FTM_SRAM4] = 4;
            bit[DRV_FTM_SRAM5] = 5;
            break;

        case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
            bit[DRV_FTM_SRAM8] = 0;
            bit[DRV_FTM_SRAM9] = 1;
            break;

        case DRV_FTM_SRAM_TBL_DSMAC_AD:
            bit[DRV_FTM_SRAM21] = 0;
            bit[DRV_FTM_SRAM23] = 1;
            bit[DRV_FTM_SRAM24] = 2;
            bit[DRV_FTM_SRAM26] = 3;
            break;

        case DRV_FTM_SRAM_TBL_DSIP_AD:
            bit[DRV_FTM_SRAM21] = 0;
            bit[DRV_FTM_SRAM22] = 1;
            bit[DRV_FTM_SRAM24] = 2;
            bit[DRV_FTM_SRAM25] = 3;
            break;

        case DRV_FTM_SRAM_TBL_USERID_AD:
            bit[DRV_FTM_SRAM22] = 0;
            bit[DRV_FTM_SRAM23] = 1;
            bit[DRV_FTM_SRAM24] = 2;
            bit[DRV_FTM_SRAM25] = 3;
            bit[DRV_FTM_SRAM26] = 4;
            break;

        case DRV_FTM_SRAM_TBL_USERID_AD1:
            bit[DRV_FTM_SRAM25] = 0;
            bit[DRV_FTM_SRAM26] = 1;
            break;

        case DRV_FTM_SRAM_TBL_NEXTHOP:
            bit[DRV_FTM_SRAM27] = 0;
            bit[DRV_FTM_SRAM28] = 1;
            bit[DRV_FTM_SRAM29] = 2;
            bit[DRV_FTM_SRAM30] = 3;
            bit[DRV_FTM_SRAM33] = 4;
            bit[DRV_FTM_SRAM34] = 5;
            break;

       case DRV_FTM_SRAM_TBL_NHOFST_MAP:
            bit[DRV_FTM_SRAM28] = 0;
            bit[DRV_FTM_SRAM31] = 1;
            bit[DRV_FTM_SRAM32] = 2;
            break;

        case DRV_FTM_SRAM_TBL_MET:
            bit[DRV_FTM_SRAM35] = 0;
            break;

        case DRV_FTM_SRAM_TBL_EDIT:
            bit[DRV_FTM_SRAM29] = 0;
            bit[DRV_FTM_SRAM30] = 1;
            bit[DRV_FTM_SRAM32] = 2;
            bit[DRV_FTM_SRAM33] = 3;
            bit[DRV_FTM_SRAM34] = 4;
            break;

        case DRV_FTM_SRAM_TBL_EDIT_OUTER:
            bit[DRV_FTM_SRAM28] = 0;
            bit[DRV_FTM_SRAM29] = 1;
            bit[DRV_FTM_SRAM30] = 2;
            bit[DRV_FTM_SRAM31] = 3;
            bit[DRV_FTM_SRAM33] = 4;
            bit[DRV_FTM_SRAM34] = 5;
            break;

       case DRV_FTM_SRAM_TBL_EDIT2:
            bit[DRV_FTM_SRAM28] = 0;
            bit[DRV_FTM_SRAM29] = 1;
            bit[DRV_FTM_SRAM30] = 2;
            bit[DRV_FTM_SRAM31] = 3;
            bit[DRV_FTM_SRAM32] = 4;
            bit[DRV_FTM_SRAM33] = 5;
            bit[DRV_FTM_SRAM34] = 6;
            break;

        case DRV_FTM_SRAM_TBL_FWD:
            bit[DRV_FTM_SRAM29] = 0;
            bit[DRV_FTM_SRAM31] = 1;
            bit[DRV_FTM_SRAM32] = 2;
            break;

        case DRV_FTM_SRAM_TBL_FWD2:
            bit[DRV_FTM_SRAM30] = 0;
            bit[DRV_FTM_SRAM31] = 1;
            bit[DRV_FTM_SRAM32] = 2;
            break;

        case DRV_FTM_SRAM_TBL_OAM_HASH_KEY:
            bit[DRV_FTM_SRAM41] = 0;
            bit[DRV_FTM_SRAM42] = 1;
            break;

        case DRV_FTM_SRAM_TBL_OAM_RMEP_KEY:
            bit[DRV_FTM_SRAM36] = 0;
            bit[DRV_FTM_SRAM37] = 1;
            break;

        case DRV_FTM_SRAM_TBL_FLOW_AD:
            bit[DRV_FTM_SRAM21] = 0;
            bit[DRV_FTM_SRAM22] = 1;
            bit[DRV_FTM_SRAM23] = 2;
            bit[DRV_FTM_SRAM24] = 3;
            break;

        case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
            bit[DRV_FTM_SRAM10] = 0;
            bit[DRV_FTM_SRAM11] = 1;
            bit[DRV_FTM_SRAM15] = 2;
            bit[DRV_FTM_SRAM16] = 3;
            bit[DRV_FTM_SRAM17] = 4;
            bit[DRV_FTM_SRAM18] = 5;
            bit[DRV_FTM_SRAM6] = 6;
            bit[DRV_FTM_SRAM7] = 7;
            break;

        case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
            bit[DRV_FTM_SRAM2] = 0;
            bit[DRV_FTM_SRAM3] = 1;
            bit[DRV_FTM_SRAM4] = 2;
            bit[DRV_FTM_SRAM5] = 3;
            bit[DRV_FTM_SRAM6] = 4;
            bit[DRV_FTM_SRAM7] = 5;
            break;

        case DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY:
            bit[DRV_FTM_SRAM17] = 0;
            bit[DRV_FTM_SRAM18] = 1;
            bit[DRV_FTM_SRAM19] = 2;
            bit[DRV_FTM_SRAM20] = 3;
            break;

        case DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY:
            bit[DRV_FTM_SRAM19] = 0;
            bit[DRV_FTM_SRAM20] = 1;
            break;

        case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
            bit[DRV_FTM_SRAM10] = 0;
            bit[DRV_FTM_SRAM11] = 1;
            bit[DRV_FTM_SRAM12] = 2;
            bit[DRV_FTM_SRAM13] = 3;
            bit[DRV_FTM_SRAM14] = 4;
            bit[DRV_FTM_SRAM15] = 5;
            break;

        case DRV_FTM_SRAM_TBL_USERID1_HASH_KEY:
            bit[DRV_FTM_SRAM14] = 0;
            bit[DRV_FTM_SRAM15] = 1;
            bit[DRV_FTM_SRAM16] = 2;
            bit[DRV_FTM_SRAM17] = 3;
            bit[DRV_FTM_SRAM18] = 4;
            break;

        case DRV_FTM_SRAM_TBL_MPLS_HASH_KEY:
            bit[DRV_FTM_SRAM10] = 0;
            bit[DRV_FTM_SRAM11] = 1;
            break;

        case DRV_FTM_SRAM_TBL_MPLS_HASH_AD:
            bit[DRV_FTM_SRAM21] = 0;
            bit[DRV_FTM_SRAM23] = 1;
            break;

        case DRV_FTM_SRAM_TBL_ANT_FLOW:
        case DRV_FTM_SRAM_TBL_ANT_FLOW2:
            bit[DRV_FTM_SRAM6] = 0;
            bit[DRV_FTM_SRAM7] = 1;
            break;

        case DRV_FTM_SRAM_TBL_XKEY:
            bit[DRV_FTM_SRAM0] = 0;
            bit[DRV_FTM_SRAM1] = 1;
            bit[DRV_FTM_SRAM2] = 2;
            bit[DRV_FTM_SRAM3] = 3;
            bit[DRV_FTM_SRAM8] = 4;
            bit[DRV_FTM_SRAM9] = 5;
            break;

        case DRV_FTM_SRAM_TBL_XKEY2:
            bit[DRV_FTM_SRAM21] = 0;
            bit[DRV_FTM_SRAM22] = 1;
            bit[DRV_FTM_SRAM25] = 2;
            bit[DRV_FTM_SRAM26] = 3;
            break;

        case DRV_FTM_SRAM_TBL_MET2:
            bit[DRV_FTM_SRAM4] = 0;
            bit[DRV_FTM_SRAM5] = 1;
            bit[DRV_FTM_SRAM6] = 2;
            bit[DRV_FTM_SRAM7] = 3;
            break;
         case DRV_FTM_SRAM_TBL_XSEC_RX:
             bit[DRV_FTM_SRAM47] = 0;
             bit[DRV_FTM_SRAM48] = 1;
             bit[DRV_FTM_SRAM49] = 2;
             bit[DRV_FTM_SRAM50] = 3;
             break;

        case DRV_FTM_SRAM_TBL_XSEC_TX:
             bit[DRV_FTM_SRAM51] = 0;
             bit[DRV_FTM_SRAM52] = 1;
             bit[DRV_FTM_SRAM53] = 2;
             bit[DRV_FTM_SRAM54] = 3;
             break;

        default:
           break;
    }

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_set_profile_fixed(uint8 lchip)
{
    uint8  table         = 0;

    /*oam table*/
    table = DRV_FTM_SRAM_TBL_OAM_RMEP_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM36, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM37, table, 0);

    table = DRV_FTM_SRAM_TBL_OAM_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM41, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM42, table, 0);

    /*Oam Mep*/
    table = DRV_FTM_SRAM_TBL_OAM_MEP;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM38, table, 0);
    /*Oam Ma*/
    table = DRV_FTM_SRAM_TBL_OAM_MA;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM39, table, 0);
    /*Oam MaName*/
    table = DRV_FTM_SRAM_TBL_OAM_MA_NAME;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM40, table, 0);

    /*ipfix hash ingress key*/
    table = DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM43, table, 0);

    /*ipfix hash egress key*/
    table = DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY1;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM44, table, 0);

    /*ipfix hash ingress ad*/
    table = DRV_FTM_SRAM_TBL_IPFIX_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM45, table, 0);

    /*ipfix hash egress ad*/
    table = DRV_FTM_SRAM_TBL_IPFIX_AD1;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM46, table, 0);

    /*XSec-Rx*/
    table = DRV_FTM_SRAM_TBL_XSEC_RX;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM47, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM48, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM49, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM50, table, 0);

    /*XSec-Tx*/
    table = DRV_FTM_SRAM_TBL_XSEC_TX;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM51, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM52, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM53, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM54, table, 0);

    /*tcam table*/
    table = DRV_FTM_TCAM_TYPE_IGS_USERID0;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY0, table);

    table = DRV_FTM_TCAM_TYPE_IGS_USERID1;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY1, table);

    table = DRV_FTM_TCAM_TYPE_IGS_USERID2;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY2, table);

    table = DRV_FTM_TCAM_TYPE_IGS_USERID3;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY3, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL0;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY4, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL1;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY5, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL2;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY6, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL3;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY7, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL4;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY8, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL5;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY9, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL6;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY10, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL7;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY11, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL8;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY12, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL9;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY13, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL10;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY14, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL11;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY15, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL12;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY16, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL13;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY17, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL14;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY18, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL15;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY19, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL16;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY20, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL17;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY21, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL18;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY22, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL19;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY23, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL20;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY24, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL21;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY25, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL22;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY26, table);

    table = DRV_FTM_TCAM_TYPE_IGS_ACL23;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY27, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL0;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY28, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL1;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY29, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL2;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY30, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL3;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY31, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL4;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY32, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL5;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY33, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL6;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY34, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL7;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY35, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL8;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY36, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL9;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY37, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL10;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY38, table);

    table = DRV_FTM_TCAM_TYPE_EGS_ACL11;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY39, table);

    table = DRV_FTM_TCAM_TYPE_EGS_SCL0;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY40, table);

    table = DRV_FTM_TCAM_TYPE_EGS_SCL1;
    DRV_FTM_ADD_FULL_KEY(DRV_FTM_TCAM_KEY41, table);
    return DRV_E_NONE;
}

static int32
_drv_at_ftm_set_profile_default(uint8 lchip)
{
    uint8  table         = 0;
    /********************************************
    dynamic edram table
    *********************************************/

    /*FIB Host0 Hash Key*/
    /* table $)Ao?=o?=J>RAMo?=D<o?=o?=o?=,o?=o?=o?=o?=FibHost0Hash o?=o?=o?=o?=Q!o?=o?=5o?=o?=RAM */
    table = DRV_FTM_SRAM_TBL_FIB0_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM8,  table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM9, table, 0);

    table = DRV_FTM_SRAM_TBL_MAC_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM0,  table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM1,  table, 0);

    /*FIB Host1 Hash Key*/
    table = DRV_FTM_SRAM_TBL_FIB1_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM16, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM17, table, 0);

    /*FLOW Hash Key*/
    table = DRV_FTM_SRAM_TBL_FLOW_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM7,  table, 1);

    /*FLOW Hash AD*/
    table = DRV_FTM_SRAM_TBL_FLOW_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM24, table, 1);

    DRV_FTM_INIT_TABLE_PART(DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, 3);
    DRV_FTM_INIT_TABLE_PART(DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, 3);
    DRV_FTM_INIT_MEM_PART(DRV_FTM_SRAM2, 2);
    DRV_FTM_INIT_MEM_PART(DRV_FTM_SRAM4, 2);
    DRV_FTM_INIT_MEM_PART(DRV_FTM_SRAM5, 2);
    /*Lpm lookup Key*/
    table = DRV_FTM_SRAM_TBL_LPM_LKP_KEY0;
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM2, table, 0, 0, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2) * 2);
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM4, table, 0, 0, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4) * 2);
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM5, table, 0, 0, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5) * 2);
    DRV_FTM_TBL_COUPLE_MODE(table) = 1;

    table = DRV_FTM_SRAM_TBL_LPM_LKP_KEY1;
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM2, table, 1, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2) * 2, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2) * 2);
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM4, table, 1, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4) * 2, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4) * 2);
    DRV_FTM_ADD_TABLE_PART(DRV_FTM_SRAM5, table, 1, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5) * 2, DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5) * 2);
    DRV_FTM_TBL_COUPLE_MODE(table) = 1;
    DRV_MEM_COUPLE(lchip, DRV_FTM_SRAM2) = 1;
    DRV_MEM_COUPLE(lchip, DRV_FTM_SRAM4) = 1;
    DRV_MEM_COUPLE(lchip, DRV_FTM_SRAM5) = 1;


    /* LB FlowTable */
    table = DRV_FTM_SRAM_TBL_ANT_FLOW;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM6, table, 1);

    /*DsIpDa*/
    table = DRV_FTM_SRAM_TBL_DSIP_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM22, table, 0);

    /*DsMac*/
    table = DRV_FTM_SRAM_TBL_DSMAC_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM23, table, 0);

    /*UserIdTunnel Hash Key*/
    table = DRV_FTM_SRAM_TBL_USERID_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM12, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM13, table, 0);

    /*UserIdTunnel Hash Key*/
    table = DRV_FTM_SRAM_TBL_USERID1_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM14, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM15, table, 0);

    /*EgrSclHash Key*/
    table = DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM18, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM19, table, 0);

    table = DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM20, table, 0);
/*
    table = DRV_FTM_SRAM_TBL_NSH_EDIT;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM20, table, 0);
*/
    /*MplsHash Key*/
    table = DRV_FTM_SRAM_TBL_MPLS_HASH_KEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM10, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM11, table, 0);
    DRV_MEM_EXT_TYPE(lchip, DRV_FTM_SRAM10) = DRV_MEM_EXT_TYPE(lchip, DRV_FTM_SRAM11) = 1;
    DRV_MEM_ENTRY_SIZE(lchip, DRV_FTM_SRAM10) = DRV_MEM_ENTRY_SIZE(lchip, DRV_FTM_SRAM11) = 64;

    g_at_ftm_master[lchip]->scl_mode = 1;

    /*UserIdTunnel AD*/
    table = DRV_FTM_SRAM_TBL_USERID_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM25, table, 0);

    /*UserIdTunnel AD*/
    table = DRV_FTM_SRAM_TBL_USERID_AD1;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM26, table, 0);

    /*MplsHash AD*/
    table = DRV_FTM_SRAM_TBL_MPLS_HASH_AD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM21, table, 0);

    /*DsNexthop*/
    table = DRV_FTM_SRAM_TBL_NEXTHOP;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM27, table, 0);

    /*NexthopMapper*/
    table = DRV_FTM_SRAM_TBL_NHOFST_MAP;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM31, table, 0);

    /*DsMet*/
    table = DRV_FTM_SRAM_TBL_MET;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM35, table, 0);

    /*DsEdit*/
    table = DRV_FTM_SRAM_TBL_EDIT;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM32, table, 0);
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM33, table, 0);

    table =DRV_FTM_SRAM_TBL_EDIT_OUTER;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM28, table, 0);

    /*XEdit*/
    table = DRV_FTM_SRAM_TBL_EDIT2;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM34, table, 0);

    /*DsFwd */
    table = DRV_FTM_SRAM_TBL_FWD;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM29, table, 0);
    /*Post DsFwd*/
    table = DRV_FTM_SRAM_TBL_FWD2;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM30, table, 0);

    /*X-Key.1*/
    table = DRV_FTM_SRAM_TBL_XKEY;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM3, table, 1);
    /*X-Key.2
    table = DRV_FTM_SRAM_TBL_XKEY2;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM26, table, 1);
    */

    /*Share Met*/
/*
    table = DRV_FTM_SRAM_TBL_MET2;
    DRV_FTM_ADD_FULL_TABLE(DRV_FTM_SRAM5, table, 0);
*/

    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_fixed(lchip));

    /*default tcam mode is private ipda+ipsa, full size, no performance*/
    g_at_ftm_master[lchip]->lpm_model = LPM_MODEL_PRIVATE_IPDA_IPSA_FULL;
    g_at_ftm_master[lchip]->nat_pbr_enable = 1;
    g_at_ftm_master[lchip]->napt_enable = 1;
    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] = (1<<(DRV_FTM_LPM_TCAM_KEY0-DRV_FTM_LPM_TCAM_KEY0)) | (1<<(DRV_FTM_LPM_TCAM_KEY1-DRV_FTM_LPM_TCAM_KEY0));
    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] = (1<<(DRV_FTM_LPM_TCAM_KEY2-DRV_FTM_LPM_TCAM_KEY0)) | (1<<(DRV_FTM_LPM_TCAM_KEY3-DRV_FTM_LPM_TCAM_KEY0));

    table = DRV_FTM_TCAM_TYPE_IGS_LPM0DA;
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY0, table);
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY1, table);
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY2, table);
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY3, table);

    table = DRV_FTM_TCAM_TYPE_IGS_LPM1;
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY4, table);
    DRV_FTM_ADD_LPM_FULL_KEY(DRV_FTM_LPM_TCAM_KEY5, table);

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_sram_tbl_name(uint32 sram_type, char* sram_tbl_id_str)
{
    char* str[DRV_FTM_SRAM_TBL_MAX] = {
        "MacHashKey",
        "FibHost0HashKey",
        "FibHost1HashKey",
        "FlowHashKey",
        "IpfixHashKey0",
        "IpfixHashKey1",
        "SclHashKey",
        "Scl1HashKey",
        "XcOamHashKey",
        "XlateHashKey",
        "Xlate1HashKey",

        "LpmLookupKey0",
        "LpmLookupKey1",
        "LpmLookupKey2",
        "LpmLookupKey3",

        "DsMacAd",
        "DsIpAd",
        "DsFlowAd",
        "IpfixHashAd",
        "IpfixHashAd1",
        "DsSclAd",
        "DsScl1Ad",

        "DsNexthop",
        "DsFwd",
        "DsMet",
        "DsEdit",

        "DsOamAps",
        "DsOamLm",
        "DsOamProtocolLm",
        "DsOamMep",
        "DsOamMa",
        "DsOamMaName",

        "MplsHashKey",
        "MplsHashAd",

        "XgponGemPort",

        "DsOamRmep",
        "DsOamKey",
        "AntFlow",
        "AntFlow2",

        "QueueHashKey",

        "DsNextHopIdMap",
        "DsFwd1",
        "DsEdit1",
        "DsXEdit",
        "DsMetExt",
        "DsXKey1",
        "DsXKey2",
        "DsXSecRx",
        "DsXSecTx",

    };

    DRV_PTR_VALID_CHECK(sram_tbl_id_str);
    if (sram_type >= DRV_FTM_SRAM_TBL_MAX)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }

    sal_strcpy(sram_tbl_id_str, str[sram_type]);

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_set_profile_user_define_edram(uint8 lchip, drv_ftm_profile_info_t *profile_info)
{
/*AT_TODO*/
    uint8 tbl_index     = 0;
    uint8 tbl_info_num  = 0;
    uint8 tbl_id        = 0;

    uint32  mem_id       = 0;
    uint8  mem_cnt      = 0;
    uint32 offset       = 0;
    uint32 entry_size   = 0;
    uint8  multi        = 0;

    /*********************************************
     dynamic edram table
     *********************************************/
    tbl_info_num = profile_info->tbl_info_size;

    for (tbl_index = 0; tbl_index < tbl_info_num; tbl_index++)
    {
        tbl_id = profile_info->tbl_info[tbl_index].tbl_id;

        if (0xFF == tbl_id)
        {
            continue;
        }

        if (DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == tbl_id && !DRV_FTM_TBL_INFO(tbl_id).sram_part_a)
        {
            DRV_FTM_INIT_TABLE_PART(DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_MAX_MEM_NUM);
            DRV_FTM_INIT_TABLE_PART(DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_MAX_MEM_NUM);
        }

        mem_cnt = 0;
        for (mem_id = 0; mem_id <= DRV_FTM_SRAM35; mem_id++)
        {
            if (!DRV_BMP_ISSET(profile_info->tbl_info[tbl_index].mem_bitmap, mem_id))
            {
                continue;
            }

            if ((tbl_id == DRV_FTM_SRAM_TBL_MET || tbl_id == DRV_FTM_SRAM_TBL_MET2))
            {
                tbl_id = (mem_id == DRV_FTM_SRAM35) ? DRV_FTM_SRAM_TBL_MET : DRV_FTM_SRAM_TBL_MET2;
            }

            mem_cnt++;
            offset       = profile_info->tbl_info[tbl_index].mem_start_offset[mem_id];
            entry_size   = profile_info->tbl_info[tbl_index].mem_entry_num[mem_id];

            if (entry_size%1024 != 0)
            {
                return DRV_E_INVALID_PARAMETER;
            }


            /* if entry size is larger than mac entry num, means couple mode*/
            if (entry_size > DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id))
            {
                if (entry_size == (2 * DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id)))
                {
                    DRV_FTM_TBL_COUPLE_MODE(tbl_id) = 1;
                }
                else
                {
                    return DRV_E_INVALID_PARAMETER;
                }
            }
            if (DRV_FTM_SRAM_TBL_ANT_FLOW == tbl_id || DRV_FTM_SRAM_TBL_ANT_FLOW2 == tbl_id
            || DRV_FTM_SRAM_TBL_FIB1_HASH_KEY == tbl_id
            || DRV_FTM_SRAM_TBL_XKEY == tbl_id || DRV_FTM_SRAM_TBL_XKEY2 == tbl_id
            || DRV_FTM_SRAM_TBL_FLOW_HASH_KEY == tbl_id
            || DRV_FTM_SRAM_TBL_USERID_AD == tbl_id
            || DRV_FTM_SRAM_TBL_USERID_AD1 == tbl_id
            || ((DRV_FTM_SRAM_TBL_USERID_HASH_KEY == tbl_id) && (DRV_FTM_SRAM10 == mem_id || DRV_FTM_SRAM11 == mem_id)))
            {
                DRV_FTM_TBL_COUPLE_MODE(tbl_id) = 1;
				entry_size = 2 * DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id);
            }

            multi = (DRV_FTM_SRAM_TBL_MPLS_HASH_KEY == tbl_id) ? 2 : 1;

            if (DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == tbl_id)
            {
                DRV_FTM_TBL_COUPLE_MODE(tbl_id) = 1;
                DRV_FTM_INIT_MEM_PART(mem_id, 2);
                DRV_FTM_ADD_TABLE_PART(mem_id, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, 0, offset, entry_size);
                DRV_FTM_ADD_TABLE_PART(mem_id, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, 1, entry_size, entry_size);
                DRV_FTM_TBL_COUPLE_MODE(DRV_FTM_SRAM_TBL_LPM_LKP_KEY1) = 1;
            }
            else
            {
                DRV_FTM_ADD_TABLE(mem_id, tbl_id, offset, entry_size*multi);
            }
            
            if (mem_id == DRV_FTM_SRAM10 || mem_id == DRV_FTM_SRAM11)
            {
                DRV_MEM_EXT_TYPE(lchip, mem_id) = (DRV_FTM_SRAM_TBL_MPLS_HASH_KEY == tbl_id) ? 1 : 0;
                DRV_MEM_ENTRY_SIZE(lchip, mem_id) = (DRV_FTM_SRAM_TBL_MPLS_HASH_KEY == tbl_id) ? 64 : 48;
            }

        }
    }
    return DRV_E_NONE;
}

#define IS_LPM_KEY_TYPE(key_type) \
  ((((key_type) == DRV_FTM_KEY_TYPE_IPV4_UCAST) || ((key_type) == DRV_FTM_KEY_TYPE_IPV6_UCAST) ||\
  ((key_type) == DRV_FTM_KEY_TYPE_IPV4_NAT) || ((key_type) == DRV_FTM_KEY_TYPE_IPV6_UCAST_HALF)) ? 1:0)

static int32
_drv_at_ftm_set_profile_user_define_lpm_tcam(uint8 lchip, drv_ftm_profile_info_t *profile_info)
{
    uint8  key_idx       = 0;
    uint8  mem_id        = 0;

    uint32 lpm_entry_size = 0;
    uint32 lpm_entry_size_v6 = 0;
    uint32 nat_entry_size = 0;
    uint32 bitmap       = 0;
    uint32 low_bmp;
    uint32 high_bmp;

    uint32 lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM1-DRV_FTM_TCAM_TYPE_IGS_LPM0DA+1] = {0};

    /********************************************
    tcam table
    *********************************************/
    for(key_idx = 0; key_idx < profile_info->key_info_size; key_idx++)
    {
        bitmap = profile_info->key_info[key_idx].tcam_bitmap[0];

        if(!IS_LPM_KEY_TYPE(profile_info->key_info[key_idx].key_id))
        {
            continue;
        }
        if (g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF
            || g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF)
        {
            low_bmp = bitmap & 0x03;  //bit 00,00,11
            high_bmp = bitmap & 0x3C; //bit 11,11,00  tcam4/5 only used by private for the 2 lpm mode.
        }
        else
        {
            low_bmp = bitmap & 0x13;  //bit 01,00,11
            high_bmp = bitmap & 0x2C; //bit 10,11,00
        }
        if(DRV_FTM_KEY_TYPE_IPV4_NAT == profile_info->key_info[key_idx].key_id)
        {
            lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM1-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
            for(mem_id = DRV_FTM_LPM_TCAM_KEY0; mem_id < DRV_FTM_LPM_TCAM_KEYM; mem_id++)
            {
                if(!DRV_IS_BIT_SET(bitmap, (mem_id - DRV_FTM_LPM_TCAM_KEY0)))
                {
                    continue;
                }
                nat_entry_size  += profile_info->key_info[key_idx].tcam_entry_num[mem_id - DRV_FTM_LPM_TCAM_KEY0];
            }
        }
        else if(DRV_FTM_KEY_TYPE_IPV6_UCAST == profile_info->key_info[key_idx].key_id)
        {
            for(mem_id = DRV_FTM_LPM_TCAM_KEY0; mem_id < DRV_FTM_LPM_TCAM_KEYM; mem_id++)
            {
                if(!DRV_IS_BIT_SET(bitmap, (mem_id - DRV_FTM_LPM_TCAM_KEY0)))
                {
                    continue;
                }
                lpm_entry_size   += profile_info->key_info[key_idx].tcam_entry_num[mem_id - DRV_FTM_LPM_TCAM_KEY0];
            }

            switch(g_at_ftm_master[lchip]->lpm_model)
            {
                case LPM_MODEL_PUBLIC_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= bitmap;
                    break;
                case LPM_MODEL_PRIVATE_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= high_bmp;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] |= low_bmp;
                    //g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][0] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][0] |= high_bmp;

                    break;
                default:
                    break;
            }
        }
        else if(DRV_FTM_KEY_TYPE_IPV6_UCAST_HALF == profile_info->key_info[key_idx].key_id)
        {
            for(mem_id = DRV_FTM_LPM_TCAM_KEY0; mem_id < DRV_FTM_LPM_TCAM_KEYM; mem_id++)
            {
                if(!DRV_IS_BIT_SET(bitmap, (mem_id - DRV_FTM_LPM_TCAM_KEY0)))
                {
                    continue;
                }
                lpm_entry_size_v6  += profile_info->key_info[key_idx].tcam_entry_num[mem_id - DRV_FTM_LPM_TCAM_KEY0];
            }

            switch(g_at_ftm_master[lchip]->lpm_model)
            {
                case LPM_MODEL_PUBLIC_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= bitmap;
                    break;
                case LPM_MODEL_PRIVATE_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= high_bmp;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] |= high_bmp;
                    break;
                default:
                    break;
            }
        }
        else if(DRV_FTM_KEY_TYPE_IPV4_UCAST == profile_info->key_info[key_idx].key_id)
        {
            for(mem_id = DRV_FTM_LPM_TCAM_KEY0; mem_id < DRV_FTM_LPM_TCAM_KEYM; mem_id++)
            {
                if(!DRV_IS_BIT_SET(bitmap, (mem_id - DRV_FTM_LPM_TCAM_KEY0)))
                {
                    continue;
                }
                lpm_entry_size   += profile_info->key_info[key_idx].tcam_entry_num[mem_id - DRV_FTM_LPM_TCAM_KEY0];
            }

            switch(g_at_ftm_master[lchip]->lpm_model)
            {
                case LPM_MODEL_PUBLIC_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= bitmap;
                    break;
                case LPM_MODEL_PRIVATE_IPDA:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= high_bmp;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= high_bmp;
                    break;
                case LPM_MODEL_PRIVATE_IPDA_IPSA_FULL:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= bitmap;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] |= bitmap;
                    break;
                case LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF:
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= low_bmp;
                    lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |= high_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2] |= low_bmp;
                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2] |= high_bmp;
                    break;
                default:
                    break;
            }
        }
    }

    if(nat_entry_size)
    {
        g_at_ftm_master[lchip]->nat_pbr_enable = 1;
    }
    else
    {
        g_at_ftm_master[lchip]->nat_pbr_enable = 0;
    }

    /*check alloced bitmap*/
    switch(g_at_ftm_master[lchip]->lpm_model)
    {
        case LPM_MODEL_PUBLIC_IPDA:
        case LPM_MODEL_PRIVATE_IPDA:
            if(lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA] |\
               lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA])
            {
                DRV_FTM_DBG_OUT("Error: In private/public ipda mode,can not alloc ipSa resource line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }
            break;

        case LPM_MODEL_PUBLIC_IPDA_IPSA_HALF:
            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA]) == 0 )
            {
                DRV_FTM_DBG_OUT("Error: In public ipda and ipsa half key mode, ipSa have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }

            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA]) == 0)
            {
                DRV_FTM_DBG_OUT("Error: In public ipda and ipsa half key mode, ipDa have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }
            break;

        case LPM_MODEL_PRIVATE_IPDA_IPSA_HALF:
            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0SA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA]) == 0 )
            {
                DRV_FTM_DBG_OUT("Error: In private ipda and ipsa half key mode, ipSa have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }

            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA]) == 0)
            {
                DRV_FTM_DBG_OUT("Error: In private ipda and ipsa half key mode, ipDa have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }
            break;

        case LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF:
        case LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF:
            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB-DRV_FTM_TCAM_TYPE_IGS_LPM0DA]) == 0)
            {
                DRV_FTM_DBG_OUT("Error:In public and private mode, public route have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }

            if((lpm_mem_bmp[DRV_FTM_TCAM_TYPE_IGS_LPM0DA-DRV_FTM_TCAM_TYPE_IGS_LPM0DA])== 0)
            {
                DRV_FTM_DBG_OUT("Error:In public and private mode, private route have no resource, line:%d\n", __LINE__);
                return DRV_E_INVALID_TCAM_ALLOC;
            }
            break;
        default:
            break;
    }

    //alloc
    for(key_idx = DRV_FTM_TCAM_TYPE_IGS_LPM0DA; key_idx <= DRV_FTM_TCAM_TYPE_IGS_LPM1; key_idx++)
    {
        bitmap = lpm_mem_bmp[key_idx-DRV_FTM_TCAM_TYPE_IGS_LPM0DA];
        for(mem_id=DRV_FTM_LPM_TCAM_KEY0; mem_id < DRV_FTM_LPM_TCAM_KEYM; mem_id++)
        {
            if(!DRV_IS_BIT_SET(bitmap, (mem_id-DRV_FTM_LPM_TCAM_KEY0)))
            {
                continue;
            }
            DRV_FTM_ADD_LPM_FULL_KEY(mem_id, key_idx);
        }
    }


    return DRV_E_NONE;
}

static int32
_drv_at_ftm_set_profile_user_define(uint8 lchip, drv_ftm_profile_info_t *profile_info)
{
    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_fixed(lchip));
    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_user_define_edram(lchip, profile_info));
    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_user_define_lpm_tcam(lchip, profile_info));

    return DRV_E_NONE;
}

int32
_drv_at_ftm_get_sram_tbl_id(uint8 lchip, uint32 sram_type, uint32* p_sram_tbl_id, uint8* p_share_num, uint8* p_per_tbl_entry_num)
{
    uint8 idx = 0;

    DRV_PTR_VALID_CHECK(p_sram_tbl_id);
    DRV_PTR_VALID_CHECK(p_share_num);

    switch (sram_type)
    {
    case DRV_FTM_SRAM_TBL_MAC_HASH_KEY:
        p_sram_tbl_id[idx++] = DsFibHost0MacHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0MacIpv4McastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0MacIpv6McastHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) =  DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
        p_sram_tbl_id[idx++] = DsFibHost0Ipv4HashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0Ipv6SingleHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0Ipv6UcastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0Ipv6McastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0TrillHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost0FcoeHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
        if(g_at_ftm_master[lchip]->napt_enable)
        {
            p_sram_tbl_id[idx++] = DsFibHost1Ipv4NatDaPortHashKey_t;
            p_sram_tbl_id[idx++] = DsFibHost1Ipv4NatSaPortHashKey_t;
            p_sram_tbl_id[idx++] = DsFibHost1Ipv6NatDaPortHashKey_t;
            p_sram_tbl_id[idx++] = DsFibHost1Ipv6NatSaPortHashKey_t;
        }

        p_sram_tbl_id[idx++] = DsFibHost1Ipv4McastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost1Ipv6McastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost1MacIpv4McastHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost1FcoeRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost1TrillMcastVlanHashKey_t;
        p_sram_tbl_id[idx++] = DsFibHost1MacIpv6McastHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
        p_sram_tbl_id[idx++] = DsFlowL2HashKey_t;
        p_sram_tbl_id[idx++] = DsFlowL2L3HashKey_t;
        p_sram_tbl_id[idx++] = DsFlowL3Ipv4HashKey_t;
        p_sram_tbl_id[idx++] = DsFlowL3Ipv6HashKey_t;
        p_sram_tbl_id[idx++] = DsFlowL3MplsHashKey_t;
        p_sram_tbl_id[idx++] = DsFlowFlexHashKey_t;
        p_sram_tbl_id[idx++] = DsFlowXKeyDoubleHashKey_t;
        p_sram_tbl_id[idx++] = DsFlowXKeyQuadHashKey_t;
        p_sram_tbl_id[idx++] = DsFlowNshForwardHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
        p_sram_tbl_id[idx++] = DsUserId0VlanPortDscpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0CvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0CvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0DoubleVlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv4PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv4SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv6PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv6SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0MacHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0MacPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv4DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0Ipv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SvlanHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SvlanMacSaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0NshHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowL2HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4RpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4UdpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4NvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4VxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6McNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6McVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelTrillMcAdjHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelTrillMcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelTrillMcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelTrillUcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelTrillUcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0EcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0IngEcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowL2UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowL3UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv4CloudSecHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6CloudSecHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowPktL2HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowPktL3HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0SclFlowPktL4HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0XKeySingleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0XKeyDoubleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId0XKeyQuadHashKey_t;
        //p_sram_tbl_id[idx++] = DsUserId0TunnelIpv6UdpHashKey_t;

        p_sram_tbl_id[idx++] = DsUserIdCvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdCvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdDoubleVlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIpv4PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIpv4SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIpv6PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIpv6SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIpv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdMacHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdMacPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSvlanHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSvlanMacSaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdNshHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSclFlowL2HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSclFlowL2UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdSclFlowL3UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4RpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4UdpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4NvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4VxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv4UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6McNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6McVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelTrillMcAdjHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelTrillMcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelTrillMcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelTrillUcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelTrillUcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdEcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdIngEcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6HashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdTunnelIpv6UdpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdXKeySingleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdXKeyDoubleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserIdXKeyQuadHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_USERID1_HASH_KEY:
        p_sram_tbl_id[idx++] = DsUserId1VlanPortDscpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1CvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1CvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1DoubleVlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv4PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv4SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv6PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv6SaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv4DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1Ipv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1MacHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1MacPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1PortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SvlanHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SvlanMacSaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1NshHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowL2HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4RpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4UdpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4NvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4VxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6McNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6McNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6McVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6McVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6UcNvgreMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6UcNvgreMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6UcVxlanMode0HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6UcVxlanMode1HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelTrillMcAdjHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelTrillMcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelTrillMcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelTrillUcDecapHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelTrillUcRpfHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1EcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1IngEcidNameSpaceHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowL2UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowL3UDFHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv4CloudSecHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6CloudSecHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowPktL2HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowPktL3HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1SclFlowPktL4HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6DaHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6GreKeyHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1VlanPortDscpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6HashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1TunnelIpv6UdpHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1XKeySingleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1XKeyDoubleHashKey_t;
        p_sram_tbl_id[idx++] = DsUserId1XKeyQuadHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY:
        p_sram_tbl_id[idx++] = DsEgressScl0CvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0CvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0DoubleVlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0PortCrossHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0PortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0PortVlanCrossHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0SvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0SvlanPortMacHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0SvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0FidDvpHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0FidDvpGroupHashKey_t,
        p_sram_tbl_id[idx++] = DsEgressScl0MetadataDvpGroupHashKey_t,
        p_sram_tbl_id[idx++] = DsEgressScl0I2eCidDvpGroupHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0VpPairHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0MetadataDvpHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl0XHashKey_t;
        p_sram_tbl_id[idx++] = DsNshEdit0_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY:
        p_sram_tbl_id[idx++] = DsEgressScl1CvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1CvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1DoubleVlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1PortCrossHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1PortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1PortVlanCrossHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1SvlanCosPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1SvlanPortMacHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1SvlanPortHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1FidDvpHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1FidDvpGroupHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1MetadataDvpGroupHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1I2eCidDvpGroupHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1VpPairHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1MetadataDvpHashKey_t;
        p_sram_tbl_id[idx++] = DsEgressScl1XHashKey_t;
        p_sram_tbl_id[idx++] = DsNshEdit1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_LPM_LKP_KEY0:
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit64Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit128Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32SnakeExt_t;
        p_sram_tbl_id[idx++] = DsNeoLpmMemorySnakeP1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit64Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit128Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32SnakeExt0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv4Bit32Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit128Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit64Snake_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv4Bit32Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit128Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit64Snake0_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0MemorySnakeP1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) =  DYNAMIC_12W_MODE;
        *p_per_tbl_entry_num = 4;
        break;

    case DRV_FTM_SRAM_TBL_LPM_LKP_KEY1:
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit64Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv6Bit128Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmIpv4Bit32SnakeExt1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmMemorySnakeP2_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv4Bit32Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit128Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0Ipv6Bit64Snake1_t;
        p_sram_tbl_id[idx++] = DsNeoLpmL0MemorySnakeP2_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_12W_MODE;
        *p_per_tbl_entry_num = 4;
        break;

    case DRV_FTM_SRAM_TBL_DSMAC_AD:
        p_sram_tbl_id[idx++] = DsMac_t;
        p_sram_tbl_id[idx++] = DsMacDefault_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) =  DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_DSIP_AD:
        p_sram_tbl_id[idx++] = DsIp_t;
        p_sram_tbl_id[idx++] = DsIpDa_t;
        p_sram_tbl_id[idx++] = DsNat_t;
        p_sram_tbl_id[idx++] = DsIpSaNat_t;
        p_sram_tbl_id[idx++] = DsFcoeDa_t;
        p_sram_tbl_id[idx++] = DsFcoeSa_t;
        p_sram_tbl_id[idx++] = DsTrillDa_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_FLOW_AD:
        p_sram_tbl_id[idx++] = DsFlow_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 2;
        break;

    case DRV_FTM_SRAM_TBL_USERID_AD:
        p_sram_tbl_id[idx++] = DsTunnelId_t;
        p_sram_tbl_id[idx++] = DsTunnelId0_t;
        p_sram_tbl_id[idx++] = DsTunnelIdHalf_t;
        p_sram_tbl_id[idx++] = DsTunnelIdHalf0_t;
        p_sram_tbl_id[idx++] = DsUserId_t;
        p_sram_tbl_id[idx++] = DsUserId0_t;
        p_sram_tbl_id[idx++] = DsUserIdHalf_t;
        p_sram_tbl_id[idx++] = DsUserIdHalf0_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_USERID_AD1:
        p_sram_tbl_id[idx++] = DsTunnelId1_t;
        p_sram_tbl_id[idx++] = DsTunnelIdHalf1_t;
        p_sram_tbl_id[idx++] = DsUserId1_t;
        p_sram_tbl_id[idx++] = DsUserIdHalf1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_NEXTHOP:
        p_sram_tbl_id[idx++] = DsNextHop4W_t;
        p_sram_tbl_id[idx++] = DsNextHop8W_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_NHOFST_MAP:
        p_sram_tbl_id[idx++] = DsNextHopIdMapPointer_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 4;
        break;

    case DRV_FTM_SRAM_TBL_FWD:
        p_sram_tbl_id[idx++] = DsFwd_t;
        p_sram_tbl_id[idx++] = DsFwdHalf_t;
        p_sram_tbl_id[idx++] = DsFwdDualHalf_t;
        p_sram_tbl_id[idx++] = DsFwd0_t;
        p_sram_tbl_id[idx++] = DsFwdHalf0_t;
        p_sram_tbl_id[idx++] = DsFwdDualHalf0_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_FWD2:
        p_sram_tbl_id[idx++] = DsFwd1_t;
        p_sram_tbl_id[idx++] = DsFwdHalf1_t;
        p_sram_tbl_id[idx++] = DsFwdDualHalf1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_MET:
        p_sram_tbl_id[idx++] = DsMet_t;
        p_sram_tbl_id[idx++] = DsMetEntry1X_t;/*AT_TODO*/
        p_sram_tbl_id[idx++] = DsMetVector1X_t;
        p_sram_tbl_id[idx++] = DsMetVector2X_t;
        p_sram_tbl_id[idx++] = DsMetVector4X_t;
        p_sram_tbl_id[idx++] = DsMetRd1X_t;
        p_sram_tbl_id[idx++] = DsMetRd2X_t;
        p_sram_tbl_id[idx++] = DsMetRd4X_t;
        p_sram_tbl_id[idx++] = DsMetEntryFitExtra_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_20W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_MET2:
        p_sram_tbl_id[idx++] = DsMetEntrySlim1X_t;
        p_sram_tbl_id[idx++] = DsMetEntryFit1X_t;
        p_sram_tbl_id[idx++] = DsMetEntryFit2X_t;
        p_sram_tbl_id[idx++] = DsMetRdSlim1X_t;
        p_sram_tbl_id[idx++] = DsMetRdSlim2X_t;
        p_sram_tbl_id[idx++] = DsMetRdSlim4X_t;
        p_sram_tbl_id[idx++] = DsMetVectorSlim1X_t;
        p_sram_tbl_id[idx++] = DsMetVectorSlim2X_t;
        p_sram_tbl_id[idx++] = DsMetVectorSlim4X_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_EDIT:
        p_sram_tbl_id[idx++] = DsEditShare0_t;

        p_sram_tbl_id[idx++] = DsL3EditAddIp40_t;
        p_sram_tbl_id[idx++] = DsL3EditAddIp60_t;
        p_sram_tbl_id[idx++] = DsL3EditAddRaw0_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp41X0_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp40_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp60_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp62X0_t;
        p_sram_tbl_id[idx++] = DsL3EditRwFlex0_t;
        p_sram_tbl_id[idx++] = DsL3EditLoopback0_t;
        p_sram_tbl_id[idx++] = DsL3EditAddTrill0_t;
        p_sram_tbl_id[idx++] = DsL3EditInsFlex0_t;
        p_sram_tbl_id[idx++] = DsL3EditDelFlex0_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls1X0_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls2X0_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls4X0_t;
        p_sram_tbl_id[idx++] = DsL3EditAddIp44X0_t;

        p_sram_tbl_id[idx++] = DsL2EditRwEth2X0_t;
        p_sram_tbl_id[idx++] = DsL2EditRwEth1X0_t;
        p_sram_tbl_id[idx++] = DsL2EditLoopback0_t;
        p_sram_tbl_id[idx++] = DsL2EditGemPort0_t;
        p_sram_tbl_id[idx++] = DsL2EditAddRaw0_t;
        p_sram_tbl_id[idx++] = DsL2EditAddEth2X0_t;
        p_sram_tbl_id[idx++] = DsL2EditAddEth1X0_t;
        p_sram_tbl_id[idx++] = DsL2EditAutoEth1X0_t;
        p_sram_tbl_id[idx++] = DsL2EditAutoEth2X0_t;

        p_sram_tbl_id[idx++] = DsL3EditAddIp6ExtHeader_t;

        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_EDIT_OUTER:
        p_sram_tbl_id[idx++] = DsEditShare1_t;

        p_sram_tbl_id[idx++] = DsL3Edit12W_t;
        p_sram_tbl_id[idx++] = DsL3Edit6W_t;
        p_sram_tbl_id[idx++] = DsL3Edit3W_t;

        p_sram_tbl_id[idx++] = DsL2Edit12WShare_t;
        p_sram_tbl_id[idx++] = DsL2Edit6WShare_t;
        p_sram_tbl_id[idx++] = DsL2Edit3WShare_t;

        p_sram_tbl_id[idx++] = DsL3EditAddIp4_t;
        p_sram_tbl_id[idx++] = DsL3EditAddIp6_t;
        p_sram_tbl_id[idx++] = DsL3EditAddRaw_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp41X_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp4_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp6_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp62X_t;
        p_sram_tbl_id[idx++] = DsL3EditRwFlex_t;
        p_sram_tbl_id[idx++] = DsL3EditLoopback_t;
        p_sram_tbl_id[idx++] = DsL3EditAddTrill_t;
        p_sram_tbl_id[idx++] = DsL3EditInsFlex_t;
        p_sram_tbl_id[idx++] = DsL3EditDelFlex_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls1X_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls2X_t;
        p_sram_tbl_id[idx++] = DsL3EditAddMpls4X_t;
        p_sram_tbl_id[idx++] = DsL3EditAddIp44X_t;
        p_sram_tbl_id[idx++] = DsL3EditAddIp6Sr_t;
        p_sram_tbl_id[idx++] = DsL3EditRwIp6Sr_t;

        p_sram_tbl_id[idx++] = DsL2EditRwEth2X_t;
        p_sram_tbl_id[idx++] = DsL2EditRwEth1X_t;
        p_sram_tbl_id[idx++] = DsL2EditLoopback_t;
        p_sram_tbl_id[idx++] = DsL2EditGemPort_t;
        p_sram_tbl_id[idx++] = DsL2EditAddRaw_t;
        p_sram_tbl_id[idx++] = DsL2EditAddEth2X_t;
        p_sram_tbl_id[idx++] = DsL2EditAddEth1X_t;
        p_sram_tbl_id[idx++] = DsL2EditAutoEth1X_t;
        p_sram_tbl_id[idx++] = DsL2EditAutoEth2X_t;


        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_OAM_HASH_KEY:
        p_sram_tbl_id[idx++] = DsOamBfdHashKey_t;
        p_sram_tbl_id[idx++] = DsOamEthHashKey_t;
        p_sram_tbl_id[idx++] = DsOamMplsLabelHashKey_t;
        p_sram_tbl_id[idx++] = DsOamMplsSectionHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_OAM_MEP:
        p_sram_tbl_id[idx++] = DsBfdMep_t;
        p_sram_tbl_id[idx++] = DsEthMep_t;
        p_sram_tbl_id[idx++] = DsBfdRmep_t;
        p_sram_tbl_id[idx++] = DsEthRmep_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_6W_MODE;
        *p_per_tbl_entry_num = 2;
        break;

    case DRV_FTM_SRAM_TBL_OAM_RMEP_KEY:
        p_sram_tbl_id[idx++] = DsEthOamRmepRmepHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_8W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_OAM_MA:
        p_sram_tbl_id[idx++] = DsMa_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_3W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_OAM_MA_NAME:
        p_sram_tbl_id[idx++] = DsMaName_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_MPLS_HASH_KEY:
        p_sram_tbl_id[idx++] = DsMplsLabelHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_MPLS_HASH_AD:
        p_sram_tbl_id[idx++] = DsMpls_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_16W_MODE;
        *p_per_tbl_entry_num = 2;
        break;

    case DRV_FTM_SRAM_TBL_ANT_FLOW:
        p_sram_tbl_id[idx++] = DsAntFlow_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_1W_MODE;
        *p_per_tbl_entry_num = 4;
        break;

    case DRV_FTM_SRAM_TBL_ANT_FLOW2:
        p_sram_tbl_id[idx++] = DsAntFlowEcmp_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_1W_MODE;
        *p_per_tbl_entry_num = 4;
        break;

    case DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY:
        p_sram_tbl_id[idx++] = DsIpfixHashKeyMem_t;
        p_sram_tbl_id[idx++] = DsIpfixL2L3HashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6HashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL2HashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4HashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6ShortHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL3MplsHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4ShortHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfShortHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixHashKeyMem0_t;
        p_sram_tbl_id[idx++] = DsIpfixL2L3HashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6HashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL2HashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4HashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6ShortHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL3MplsHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4ShortHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfShortHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeyDoubleHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeySingleHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeyQuadHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixNshHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixNshShortHashKey_t;
        p_sram_tbl_id[idx++] = DsIpfixNshHashKey0_t;
        p_sram_tbl_id[idx++] = DsIpfixNshShortHashKey0_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_20W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

   case DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY1:
        p_sram_tbl_id[idx++] = DsIpfixHashKeyMem1_t;
        p_sram_tbl_id[idx++] = DsIpfixL2L3HashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6HashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL2HashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4HashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv6ShortHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL3MplsHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixL3Ipv4ShortHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixUdfShortHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeyDoubleHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeySingleHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixXKeyQuadHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixNshHashKey1_t;
        p_sram_tbl_id[idx++] = DsIpfixNshShortHashKey1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_20W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_IPFIX_AD:
        p_sram_tbl_id[idx++] = DsIpfixSessionRecordMem0_t;
        p_sram_tbl_id[idx++] = DsIpfixSessionRecord0_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_9W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_IPFIX_AD1:
        p_sram_tbl_id[idx++] = DsIpfixSessionRecordMem1_t;
        p_sram_tbl_id[idx++] = DsIpfixSessionRecord1_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_9W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_EDIT2:
         p_sram_tbl_id[idx++] = DsEditShare2_t;
        p_sram_tbl_id[idx++] = DsXEdit3W_t;
        p_sram_tbl_id[idx++] = DsXEdit6W_t;
        p_sram_tbl_id[idx++] = DsXEdit12W_t;
        p_sram_tbl_id[idx++] = DsXEditDelFlex_t;
        p_sram_tbl_id[idx++] = DsXEditInsFlex_t;
        p_sram_tbl_id[idx++] = DsXEditRwFlex_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_XKEY:
        p_sram_tbl_id[idx++] = DsXLookup0HashKey_t;
        p_sram_tbl_id[idx++] = DsXLookup0MutationHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_12W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_XKEY2:
        p_sram_tbl_id[idx++] = DsXLookup1HashKey_t;

        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_4U_16W_MODE;
        *p_per_tbl_entry_num = 1;
        break;
    case DRV_FTM_SRAM_TBL_XSEC_RX:
        p_sram_tbl_id[idx++] = DsXSecRxL2BasicHashKey_t;
        p_sram_tbl_id[idx++] = DsXSecRxL2MacsecHashKey_t;
        p_sram_tbl_id[idx++] = DsXSecRxL3L4V4HashKey_t;
        p_sram_tbl_id[idx++] = DsXSecRxL3L4V6HashKey_t;
        p_sram_tbl_id[idx++] = DsXSecRxSpiHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_2U_8W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    case DRV_FTM_SRAM_TBL_XSEC_TX:
        p_sram_tbl_id[idx++] = DsXSecTxL2BasicHashKey_t;
        p_sram_tbl_id[idx++] = DsXSecTxL3L4V4HashKey_t;
        p_sram_tbl_id[idx++] = DsXSecTxL3L4V6HashKey_t;
        p_sram_tbl_id[idx++] = DsXSecTxSpiHashKey_t;
        DRV_FTM_TBL_ACCESS_FLAG(sram_type) = DYNAMIC_2U_8W_MODE;
        *p_per_tbl_entry_num = 1;
        break;

    default:
        return DRV_E_INVAILD_TYPE;
    }

    *p_share_num = idx;

    return DRV_E_NONE;
}

int32
_drv_at_ftm_get_edram_bitmap(uint8 lchip, uint8 sram_type, uint32* bitmap, uint32* sram_array)
{
    uint32 bit_map_temp = 0;
    uint8 mem_id        = 0;
    uint8 idx           = 0;
    uint32 bit[DRV_FTM_EDRAM_MAX]     = {0};

    __drv_at_ftm_get_edram_bitmap(lchip, sram_type, bit);
    for (mem_id = DRV_FTM_SRAM0; mem_id < DRV_FTM_EDRAM_MAX; mem_id++)
    {
        if (DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(sram_type), mem_id) && DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, mem_id))
        {
            idx = bit[mem_id];
            DRV_BIT_SET(bit_map_temp, idx);
            sram_array[idx] = mem_id;
        }
    }
    *bitmap = bit_map_temp;

    return DRV_E_NONE;
}

static int32
_sys_usw_ftm_get_hash_type(uint8 lchip,
                           uint8 sram_type,
                           uint32 mem_id,
                           uint8 couple,
                           uint32 *poly)
{
    drv_ftm_hash_poly_t* p_hash_poly = &g_at_ftm_master[lchip]->p_sram_tbl_info[sram_type].hash_poly;
    uint32 sram_index = 0;

    *poly = 0;
    for (sram_index=0;sram_index<p_hash_poly->sram_num;sram_index++)
    {
        if (mem_id == p_hash_poly->sram_poly[sram_index].sram_id)
        {
            *poly = p_hash_poly->sram_poly[sram_index].poly_map[couple].drv_poly;
            break;
        }
    }

    return DRV_E_NONE;
}

static tbls_ext_info_t*
_drv_at_ftm_build_dynamic_tbl_info()
{
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    dynamic_mem_ext_content_t* p_dyn_mem_ext_info = NULL;

    p_tbl_ext_info = mem_malloc(MEM_FTM_MODULE, sizeof(tbls_ext_info_t));
    if (NULL == p_tbl_ext_info)
    {
        return NULL;
    }

    sal_memset(p_tbl_ext_info, 0, sizeof(tbls_ext_info_t));

    p_dyn_mem_ext_info = mem_malloc(MEM_FTM_MODULE, sizeof(dynamic_mem_ext_content_t));
    if (NULL == p_dyn_mem_ext_info)
    {
        mem_free(p_tbl_ext_info);
        return NULL;
    }

    sal_memset(p_dyn_mem_ext_info, 0, sizeof(dynamic_mem_ext_content_t));

    p_tbl_ext_info->ptr_ext_content = p_dyn_mem_ext_info;

    return p_tbl_ext_info;

}
 extern uint32 _drv_usw_consum_hw_addr_size(uint16 word_num);

/*
DsNeoLpmIpv4Bit32SnakeExt_t/DsNeoLpmIpv4Bit32SnakeExt1_t/DsNeoLpmIpv4Bit32SnakeExt0_t
used as L0
*/
#define LPM_L0_TBL_ID_CHK(tbl_id) (DsNeoLpmL0Ipv4Bit32Snake_t == tbl_id || DsNeoLpmL0Ipv6Bit128Snake_t == tbl_id \
                                                   || DsNeoLpmL0Ipv6Bit64Snake_t == tbl_id || DsNeoLpmL0Ipv4Bit32Snake0_t == tbl_id \
                                                   || DsNeoLpmL0Ipv6Bit128Snake0_t == tbl_id || DsNeoLpmL0Ipv6Bit64Snake0_t == tbl_id \
                                                   || DsNeoLpmL0MemorySnakeP1_t == tbl_id || DsNeoLpmL0Ipv4Bit32Snake1_t == tbl_id \
                                                   || DsNeoLpmL0Ipv6Bit128Snake1_t == tbl_id || DsNeoLpmL0Ipv6Bit64Snake1_t == tbl_id \
                                                   || DsNeoLpmL0MemorySnakeP2_t == tbl_id || DsNeoLpmIpv4Bit32SnakeExt_t == tbl_id  \
                                                   || DsNeoLpmIpv4Bit32SnakeExt1_t == tbl_id || DsNeoLpmIpv4Bit32SnakeExt0_t == tbl_id)
#define LPM_L0_MEM_ID_CHK(mem_id) (DRV_FTM_SRAM2 == mem_id || DRV_FTM_SRAM3 == mem_id)

static int32
_drv_at_ftm_alloc_dyn_share_tbl(uint8 lchip, uint8 sram_type, tbls_id_t tbl_id, uint8 per_tbl_entry_num)
{
    uint32 bitmap = 0;
    uint32 sram_array[16] = {0};
    uint8   bit_idx = 0;

    uint32 mem_entry_num = 0;
    uint32 max_index_num = 0;
    uint32 start_index = 0;
    uint32 end_index = 0;


    uint32 start_base = 0;
    uint32 end_base = 0;
    uint32 entry_num = 0;

    uint32 hw_base = 0;
    uint32 tbl_offset = 0;
    int8   mem_id = 0;
    uint8 i = 0;
    dynamic_mem_ext_content_t* p_dyn_mem_ext_info = NULL;
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    drv_ftm_sram_id_info_t* p_sram_node = NULL;

    if (0 == DRV_FTM_TBL_MAX_ENTRY_NUM(sram_type))
    {
        return DRV_E_NONE;
    }

    if (!TABLE_EXT_INFO_PTR(lchip, tbl_id))
    {
        p_tbl_ext_info = _drv_at_ftm_build_dynamic_tbl_info();
        if (NULL == p_tbl_ext_info)
        {
            return DRV_E_NO_MEMORY;
        }
        TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;
        TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;
    }
    else
    {
        max_index_num = TABLE_MAX_INDEX(lchip, tbl_id);
    }


    p_dyn_mem_ext_info = DYNAMIC_EXT_INFO_PTR(lchip, tbl_id);
    TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_DYNAMIC;
    p_dyn_mem_ext_info->dynamic_access_mode = DYNAMIC_DEFAULT;

    p_dyn_mem_ext_info->dynamic_access_mode = DRV_FTM_TBL_ACCESS_FLAG(sram_type);
    p_dyn_mem_ext_info->dynamic_mem_allocate_info.mem_size =  ((DYNAMIC_ACCESS_MODE(lchip, tbl_id)&0xFF)*DRV_BYTES_PER_WORD);
    p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_num =  ((DYNAMIC_ACCESS_MODE(lchip, tbl_id)>>DYNAMIC_ACCESS_UNIT_NUM_SHIFT)&0xFF);

   if(p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_num == 0)
   {
      p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_num =   DYNAMIC_MEM_SIZE(lchip, tbl_id) /TABLE_ENTRY_SIZE(lchip, tbl_id);
      p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_size = TABLE_ENTRY_SIZE(lchip, tbl_id);
   }
   else
  {
     p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_size = p_dyn_mem_ext_info->dynamic_mem_allocate_info.mem_size /p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_num;

   }
   TABLE_INFO_PTR(lchip, tbl_id)->entry_offset = (_drv_usw_consum_hw_addr_size(DYNAMIC_ACCESS_MODE(lchip, tbl_id)&0xFF) << 2);

   if ((TABLE_OP_TYPE(lchip, tbl_id) & Op_DisWriteMask) || (p_dyn_mem_ext_info->dynamic_mem_allocate_info.unit_num == 1))
   {
       TABLE_IOCTL_TYPE(lchip, tbl_id)  = DRV_TBL_TYPE_DYN;
   }
   else
   {
       TABLE_IOCTL_TYPE(lchip, tbl_id)  = DRV_TBL_TYPE_DYN_MASK;
   }
   
     DRV_BMP_ITER_BEGIN(DRV_FTM_TBL_MEM_BITMAP(sram_type), bit_idx)
    {
        if (DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == sram_type
            || DRV_FTM_SRAM_TBL_LPM_LKP_KEY1 == sram_type)
        {
            if ((LPM_L0_TBL_ID_CHK(tbl_id) && !LPM_L0_MEM_ID_CHK(bit_idx))
                || (!LPM_L0_TBL_ID_CHK(tbl_id) && LPM_L0_MEM_ID_CHK(bit_idx)))
            {
                continue;
            }
        }
        DRV_BMP_SET(DYNAMIC_BITMAP(lchip, tbl_id), bit_idx);
    }
    DRV_BMP_ITER_END(DRV_FTM_TBL_MEM_BITMAP(sram_type), bit_idx);

    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);


    for (bit_idx = 0; bit_idx < (sizeof(sram_array)/sizeof(sram_array[0])); bit_idx++)
    {
        if (!DRV_IS_BIT_SET(bitmap, bit_idx))
        {
            continue;
        }

        mem_id = sram_array[bit_idx];
        DRV_FTM_SRAM_DB(mem_id).connect_id = bit_idx;
        if (DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == sram_type
            || DRV_FTM_SRAM_TBL_LPM_LKP_KEY1 == sram_type)
        {
            uint8 part_id = 0;
            if ((LPM_L0_TBL_ID_CHK(tbl_id) && bit_idx >= 2)
                || (!LPM_L0_TBL_ID_CHK(tbl_id) && bit_idx < 2))
            {
                continue;
            }
            part_id = DRV_FTM_TBL_INFO(sram_type).sram_part_a[DRV_FTM_SRAM_DB(mem_id).block_id];
            mem_entry_num = DRV_FTM_SRAM_DB(mem_id).part[part_id].entry_num;
        }
        else
        {
            mem_entry_num = DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, mem_id);
        }

        if (DsAntFlow_t == tbl_id || DsMplsLabelHashKey_t == tbl_id || ((DsXLookup0HashKey_t == tbl_id || DsXLookup0MutationHashKey_t == tbl_id) && mem_id > 3))
        {
            hw_base = DRV_MEM_ADD6W(lchip, mem_id);
        }
        else
        {
            hw_base = DRV_MEM_ADD3W(lchip, mem_id);
        }

        DYNAMIC_ENTRY_NUM(lchip, tbl_id, mem_id) = mem_entry_num;
        tbl_offset = DRV_FTM_TBL_MEM_START_OFFSET(sram_type, mem_id);

        if (sram_type == DRV_FTM_SRAM_TBL_LPM_LKP_KEY0
            || sram_type == DRV_FTM_SRAM_TBL_LPM_LKP_KEY1)
        {
            uint8 sram_index = 0;
            uint8 part_id = 0;
            do {
                if (DRV_FTM_TBL_INFO(sram_type).sram_id_a[sram_index] == mem_id)
                {
                    break;
                }
            }while(++sram_index<DRV_FTM_TBL_INFO(sram_type).sram_num);
            part_id = DRV_FTM_TBL_INFO(sram_type).sram_part_a[sram_index];
            tbl_offset = DRV_FTM_SRAM_DB(mem_id).part[part_id].mem_offset;
            DYNAMIC_DATA_BASE(lchip, tbl_id, mem_id, 0) = hw_base + (tbl_offset/per_tbl_entry_num/2) *  TABLE_INFO_PTR(lchip, tbl_id)->entry_offset;
        }
        else
        {
            DYNAMIC_DATA_BASE(lchip, tbl_id, mem_id, 0) = hw_base + (tbl_offset/per_tbl_entry_num) *  TABLE_INFO_PTR(lchip, tbl_id)->entry_offset;
        }
        start_index = max_index_num; /*per key index*/
        start_base = entry_num; /*per 80bit base*/
        entry_num += mem_entry_num;

        if (DsAntFlow_t == tbl_id || DsAntFlowEcmp_t == tbl_id)
        {
            max_index_num += (mem_entry_num/4)*8;
        }
        else if (sram_type == DRV_FTM_SRAM_TBL_LPM_LKP_KEY0
            || sram_type == DRV_FTM_SRAM_TBL_LPM_LKP_KEY1)
        {
            max_index_num += mem_entry_num/per_tbl_entry_num/2;
        }
        else
        {
            max_index_num += mem_entry_num/per_tbl_entry_num;
        }

        end_index = (max_index_num - 1);
        end_base = entry_num - 1;

        DYNAMIC_START_INDEX(lchip, tbl_id, mem_id) = start_index;
        DYNAMIC_END_INDEX(lchip, tbl_id, mem_id) = end_index;


        DYNAMIC_TABLE_START(lchip, tbl_id, i) = DYNAMIC_START_INDEX(lchip, tbl_id, mem_id);
        DYNAMIC_TABLE_END(lchip, tbl_id, i) = DYNAMIC_END_INDEX(lchip, tbl_id, mem_id);
        DYNAMIC_TABLE_BLK_ID(lchip, tbl_id, i) = mem_id;
        i++;

        p_sram_node = _drv_at_ftm_get_sram_db_node(lchip, sram_type, bit_idx);
        if (p_sram_node)
        {
            p_sram_node->min_index = start_base;
            p_sram_node->max_index = end_base;
        }
    }

    DYNAMIC_TABLE_BLK_NUM(lchip, tbl_id) = i;
    TABLE_EXT_INFO(lchip, tbl_id).entry = max_index_num;
    TABLE_INFO(lchip, tbl_id).entry = 0;

    DRV_FTM_TBL_BASE_BITMAP(sram_type) = bitmap;

    for (bit_idx = 0; bit_idx < DRV_FTM_MAX_MEM_NUM; bit_idx++)
    {
        if (DRV_IS_BIT_SET(bitmap, bit_idx))
        {
            mem_id = sram_array[bit_idx];
            TABLE_EXT_INFO(lchip, tbl_id).addrs[0] = DYNAMIC_DATA_BASE(lchip, tbl_id, mem_id, 0);
            break;
        }
    }

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_alloc_sram(uint8 lchip)
{
    uint8 index = 0;
    uint32 sram_type = 0;
    uint32 sram_tbl_id = MaxTblId_t;
    uint32 sram_tbl_a[200] = {0};
    uint8  share_tbl_num  = 0;
    uint8  per_tbl_entry_num = 0;
    uint32 max_entry_num = 0;

    for (sram_type = 0; sram_type < DRV_FTM_SRAM_TBL_MAX; sram_type++)
    {
        max_entry_num = DRV_FTM_TBL_MAX_ENTRY_NUM(sram_type);
        if (0 == max_entry_num)
        {
            continue;
        }

        _drv_at_ftm_get_sram_tbl_id(lchip, sram_type, sram_tbl_a, &share_tbl_num, &per_tbl_entry_num);

        for (index = 0; index < share_tbl_num; index++)
        {
            sram_tbl_id = sram_tbl_a[index];

            if (sram_tbl_id >= MaxTblId_t)
            {
                DRV_FTM_DBG_DUMP("unexpect tbl id:%d\r\n", sram_tbl_id);
                return DRV_E_INVAILD_TYPE;
            }

            if ((NULL == TABLE_INFO_PTR(lchip, sram_tbl_id)) || 0 == TABLE_FIELD_NUM(lchip, sram_tbl_id))
            {
                continue;
            }
            DRV_IF_ERROR_RETURN(_drv_at_ftm_alloc_dyn_share_tbl(lchip, sram_type, sram_tbl_id, per_tbl_entry_num));
            if (DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY == sram_type
                || DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY == sram_type)
            {
                TABLE_EXT_TYPE(lchip, sram_tbl_id) = 3;
            }
        }
        index = 0;
    }
    TABLE_IOCTL_TYPE(lchip, DsEthMep_t) = DRV_TBL_TYPE_OAM;
    TABLE_IOCTL_TYPE(lchip, DsEthRmep_t) = DRV_TBL_TYPE_OAM;
    TABLE_IOCTL_TYPE(lchip, DsBfdMep_t) = DRV_TBL_TYPE_OAM;
    TABLE_IOCTL_TYPE(lchip, DsBfdRmep_t) = DRV_TBL_TYPE_OAM;
    if (TABLE_MAX_INDEX(lchip, DsMetEntrySlim1X_t))
    {
        TABLE_IOCTL_TYPE(lchip, DsMetEntrySlim1X_t) = DRV_TBL_TYPE_MET_SLIM;
        TABLE_IOCTL_TYPE(lchip, DsMetVectorSlim1X_t) = DRV_TBL_TYPE_MET_SLIM;
        TABLE_IOCTL_TYPE(lchip, DsMetVectorSlim2X_t) = DRV_TBL_TYPE_MET_SLIM;
        TABLE_IOCTL_TYPE(lchip, DsMetVectorSlim4X_t) = DRV_TBL_TYPE_MET_SLIM;
    }

    TABLE_IOCTL_TYPE(lchip, TsRcCtl_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcDelayLineCfg_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcDuraCntShadow_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcLocalTsShadow_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcNsCarryFlag_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcNsCntCarryThreshold_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcNsCntShadow_t) = DRV_TBL_TYPE_RTC;
    /*TABLE_IOCTL_TYPE(lchip, TsRcNsCntShiftCfg_t) = DRV_TBL_TYPE_RTC; EMU_TODO*/
    TABLE_IOCTL_TYPE(lchip, TsRcQuantaDriftDuraShadow_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcQuantaDriftShadow_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcResidualCfg_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcSecCntShadow_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, TsRcSyncMonitor_t) = DRV_TBL_TYPE_RTC;
    TABLE_IOCTL_TYPE(lchip, IpeFwdCtl_t) = DRV_TBL_TYPE_HOOK;
    TABLE_IOCTL_TYPE(lchip, IpeHeaderAdjustCtl_t) = DRV_TBL_TYPE_HOOK;

    /* LPM */
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv4Bit32Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv6Bit64Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv6Bit128Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv4Bit32SnakeExt_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv4Bit32Snake1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv6Bit64Snake1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmL0Ipv6Bit128Snake1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv4Bit32SnakeExt1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv4Bit32Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv6Bit64Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv6Bit128Snake_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv4Bit32Snake1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv6Bit64Snake1_t) = DRV_TBL_TYPE_DYN_LPM;
    TABLE_IOCTL_TYPE(lchip, DsNeoLpmIpv6Bit128Snake1_t) = DRV_TBL_TYPE_DYN_LPM;

    return DRV_E_NONE;
}

#define ___change_table_config
static int32
_drv_at_ftm_get_tcam_info(uint8 lchip,
                                 uint32 tcam_key_type,
                                 uint32* p_tcam_key_id,
                                 uint32* p_tcam_ad_tbl,
                                 uint8* p_key_share_num,
                                 uint8* p_ad_share_num)
{
    uint8 idx0 = 0;
    uint8 idx1 = 0;

    DRV_PTR_VALID_CHECK(p_tcam_key_id);
    DRV_PTR_VALID_CHECK(p_tcam_ad_tbl);
    DRV_PTR_VALID_CHECK(p_key_share_num);
    DRV_PTR_VALID_CHECK(p_ad_share_num);

    switch (tcam_key_type)
    {
    case DRV_FTM_TCAM_TYPE_IGS_ACL0:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam0_t;
        p_tcam_ad_tbl[idx1++] = DsAcl0Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl0_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL1:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam1_t;
        p_tcam_ad_tbl[idx1++] = DsAcl1Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl1_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL2:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam2_t;
        p_tcam_ad_tbl[idx1++] = DsAcl2Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl2_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL3:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam3_t;
        p_tcam_ad_tbl[idx1++] = DsAcl3Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl3_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL4:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam4_t;
        p_tcam_ad_tbl[idx1++] = DsAcl4Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl4_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL5:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam5_t;
        p_tcam_ad_tbl[idx1++] = DsAcl5Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl5_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL6:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam6_t;
        p_tcam_ad_tbl[idx1++] = DsAcl6Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl6_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL7:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam7_t;
        p_tcam_ad_tbl[idx1++] = DsAcl7Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl7_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL8:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam8_t;
        p_tcam_ad_tbl[idx1++] = DsAcl8Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl8_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL9:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam9_t;
        p_tcam_ad_tbl[idx1++] = DsAcl9Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl9_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL10:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam10_t;
        p_tcam_ad_tbl[idx1++] = DsAcl10Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl10_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL11:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam11_t;
        p_tcam_ad_tbl[idx1++] = DsAcl11Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl11_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL12:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam12_t;
        p_tcam_ad_tbl[idx1++] = DsAcl12Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl12_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL13:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam13_t;
        p_tcam_ad_tbl[idx1++] = DsAcl13Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl13_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL14:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam14_t;
        p_tcam_ad_tbl[idx1++] = DsAcl14Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl14_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL15:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam15_t;
        p_tcam_ad_tbl[idx1++] = DsAcl15Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl15_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL16:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam16_t;
        p_tcam_ad_tbl[idx1++] = DsAcl16Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl16_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL17:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam17_t;
        p_tcam_ad_tbl[idx1++] = DsAcl17Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl17_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL18:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam18_t;
        p_tcam_ad_tbl[idx1++] = DsAcl18Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl18_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL19:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam19_t;
        p_tcam_ad_tbl[idx1++] = DsAcl19Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl19_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL20:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam20_t;
        p_tcam_ad_tbl[idx1++] = DsAcl20Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl20_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL21:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam21_t;
        p_tcam_ad_tbl[idx1++] = DsAcl21Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl21_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL22:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam22_t;
        p_tcam_ad_tbl[idx1++] = DsAcl22Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl22_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_ACL23:
        p_tcam_key_id[idx0++] = DsProgrammingAclTcam23_t;
        p_tcam_ad_tbl[idx1++] = DsAcl23Ingress_t;
        p_tcam_ad_tbl[idx1++] = DsIpeAcl23_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL0:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam0_t;
        p_tcam_ad_tbl[idx1++] = DsAcl0Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl0_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL1:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam1_t;
        p_tcam_ad_tbl[idx1++] = DsAcl1Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl1_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL2:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam2_t;
        p_tcam_ad_tbl[idx1++] = DsAcl2Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl2_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL3:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam3_t;
        p_tcam_ad_tbl[idx1++] = DsAcl3Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl3_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL4:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam4_t;
        p_tcam_ad_tbl[idx1++] = DsAcl4Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl4_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL5:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam5_t;
        p_tcam_ad_tbl[idx1++] = DsAcl5Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl5_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL6:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam6_t;
        p_tcam_ad_tbl[idx1++] = DsAcl6Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl6_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL7:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam7_t;
        p_tcam_ad_tbl[idx1++] = DsAcl7Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl7_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL8:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam8_t;
        p_tcam_ad_tbl[idx1++] = DsAcl8Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl8_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL9:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam9_t;
        p_tcam_ad_tbl[idx1++] = DsAcl9Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl9_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL10:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam10_t;
        p_tcam_ad_tbl[idx1++] = DsAcl10Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl10_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL11:
        p_tcam_key_id[idx0++] = DsEgrProgrammingAclTcam11_t;
        p_tcam_ad_tbl[idx1++] = DsAcl11Egress_t;
        p_tcam_ad_tbl[idx1++] = DsEpeAcl11_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_USERID0:
        p_tcam_key_id[idx0++] = DsSclHash0ConflictTcamSize0_t;
        p_tcam_key_id[idx0++] = DsSclHash0ConflictTcamSize1_t;
        p_tcam_key_id[idx0++] = DsSclHash0ConflictTcamSize2_t;

        p_tcam_ad_tbl[idx1++] = DsUserId0Tcam_t;
        p_tcam_ad_tbl[idx1++] = DsUserIdHalfTcam0_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelId0Tcam_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelIdHalfTcam0_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_USERID1:
        p_tcam_key_id[idx0++] = DsSclHash1ConflictTcamSize0_t;
        p_tcam_key_id[idx0++] = DsSclHash1ConflictTcamSize1_t;
        p_tcam_key_id[idx0++] = DsSclHash1ConflictTcamSize2_t;

        p_tcam_ad_tbl[idx1++] = DsUserId1Tcam_t;
        p_tcam_ad_tbl[idx1++] = DsUserIdHalfTcam1_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelId1Tcam_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelIdHalfTcam1_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_USERID2:
        p_tcam_key_id[idx0++] = DsScl0ExtTypeDataKey160_t;
        p_tcam_key_id[idx0++] = DsScl0MacKey160_t;
        p_tcam_key_id[idx0++] = DsScl0L3Key160_t;
        p_tcam_key_id[idx0++] = DsScl0Ipv6Key320_t;
        p_tcam_key_id[idx0++] = DsScl0MacL3Key320_t;
        p_tcam_key_id[idx0++] = DsScl0MacIpv6Key640_t;
        p_tcam_key_id[idx0++] = DsScl0UdfKey160_t;
        p_tcam_key_id[idx0++] = DsScl0UdfKey320_t;
        p_tcam_key_id[idx0++] = DsScl0UdfKey640_t;
        p_tcam_key_id[idx0++] = DsScl0PktL2Key320_t;
        p_tcam_key_id[idx0++] = DsScl0PktL3L4Key640_t;
        p_tcam_key_id[idx0++] = DsScl2MacKey160_t;
        p_tcam_key_id[idx0++] = DsScl2L3Key160_t;
        p_tcam_key_id[idx0++] = DsScl2Ipv6Key320_t;
        p_tcam_key_id[idx0++] = DsScl2MacL3Key320_t;
        p_tcam_key_id[idx0++] = DsScl2MacIpv6Key640_t;
        p_tcam_key_id[idx0++] = DsScl2UdfKey160_t;
        p_tcam_key_id[idx0++] = DsScl2UdfKey320_t;
        p_tcam_ad_tbl[idx1++] = DsUserId2_t;

        p_tcam_ad_tbl[idx1++] = DsUserId0FlowTcam_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelId0FlowTcam_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeySingle0_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeyDouble0_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeyQuad0_t;

        break;

    case DRV_FTM_TCAM_TYPE_IGS_USERID3:
        p_tcam_key_id[idx0++] = DsScl1ExtTypeDataKey160_t;
        p_tcam_key_id[idx0++] = DsScl1MacKey160_t;
        p_tcam_key_id[idx0++] = DsScl1L3Key160_t;
        p_tcam_key_id[idx0++] = DsScl1Ipv6Key320_t;
        p_tcam_key_id[idx0++] = DsScl1MacL3Key320_t;
        p_tcam_key_id[idx0++] = DsScl1MacIpv6Key640_t;
        p_tcam_key_id[idx0++] = DsScl1UdfKey160_t;
        p_tcam_key_id[idx0++] = DsScl1UdfKey320_t;
        p_tcam_key_id[idx0++] = DsScl1UdfKey640_t;
        p_tcam_key_id[idx0++] = DsScl1PktL2Key320_t;
        p_tcam_key_id[idx0++] = DsScl1PktL3L4Key640_t;

        p_tcam_key_id[idx0++] = DsScl3MacKey160_t;
        p_tcam_key_id[idx0++] = DsScl3L3Key160_t;
        p_tcam_key_id[idx0++] = DsScl3Ipv6Key320_t;
        p_tcam_key_id[idx0++] = DsScl3MacL3Key320_t;
        p_tcam_key_id[idx0++] = DsScl3MacIpv6Key640_t;
        p_tcam_key_id[idx0++] = DsScl3UdfKey160_t;
        p_tcam_key_id[idx0++] = DsScl3UdfKey320_t;
        p_tcam_ad_tbl[idx1++] = DsUserId3_t;

        p_tcam_ad_tbl[idx1++] = DsUserId1FlowTcam_t;
        p_tcam_ad_tbl[idx1++] = DsTunnelId1FlowTcam_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeySingle1_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeyDouble1_t;
        p_tcam_key_id[idx0++] = TempSclTcamXKeyQuad1_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_SCL0:
        p_tcam_key_id[idx0++] = DsEgressScl0TcamKey_t;
        p_tcam_ad_tbl[idx1++] = DsEgressScl0TcamAd_t;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_SCL1:
        p_tcam_key_id[idx0++] = DsEgressScl1TcamKey_t;
        p_tcam_ad_tbl[idx1++] = DsEgressScl1TcamAd_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM_ALL:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4HalfKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6DoubleKey0_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6SingleKey_t;

        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SingleKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4HalfKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6DoubleKey0Ad_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM0DA:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4HalfKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6DoubleKey0_t;

        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6DoubleKey0Ad_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4HalfKeyAd_t;

        if (g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1])
        {
            p_tcam_key_id[idx0++] = DsLpmTcamIpv6SingleKey_t;
            p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SingleKeyAd_t;
        }
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM0SA:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4SaHalfKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6SaDoubleKey0_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4SaHalfKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SaDoubleKey0Ad_t;
        if(g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1])
        {
            p_tcam_key_id[idx0++] = DsLpmTcamIpv6SaSingleKey_t;
            p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SaSingleKeyAd_t;
        }
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4DaPubHalfKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6DaPubDoubleKey0_t;

        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4DaPubHalfKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6DaPubDoubleKey0Ad_t;
        if(g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1])
        {
            p_tcam_key_id[idx0++] = DsLpmTcamIpv6DaPubSingleKey_t;
            p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6DaPubSingleKeyAd_t;
        }
        p_tcam_ad_tbl[idx1++] =  DsLpmTcamIpv4DaPubRouteKeyAd_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4SaPubHalfKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6SaPubDoubleKey0_t;

        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4SaPubHalfKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SaPubDoubleKey0Ad_t;
        if(g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1])
        {
            p_tcam_key_id[idx0++] = DsLpmTcamIpv6SaPubSingleKey_t;
            p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6SaPubSingleKeyAd_t;
        }
        p_tcam_ad_tbl[idx1++] =  DsLpmTcamIpv4SaPubRouteKeyAd_t;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_LPM1:
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4NatDoubleKey_t;
        p_tcam_key_id[idx0++] = DsLpmTcamIpv4DoubleKey_t;
#ifdef  ARCTIC_C
        p_tcam_key_id[idx0++] = DsLpmTcamIpv6DoubleKey1_t;
#endif
        p_tcam_key_id[idx0++] = TempDsLpmTcamIpv6NatDoubleKey_t;

        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv4NatDoubleKeyAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamAd_t;   /*special for DsLpmTcamIpv4DoubleKey_t */
        p_tcam_ad_tbl[idx1++] = DsNatTcamAd_t;
        p_tcam_ad_tbl[idx1++] = DsLpmTcamIpv6NatDoubleKeyAd_t;
        break;

    case DRV_FTM_TCAM_TYPE_STATIC_TCAM:
        p_tcam_key_id[idx0++] = DsCategoryIdPairTcamKey_t;
        p_tcam_key_id[idx0++] = DsLtidSelectTcam_t;
        p_tcam_key_id[idx0++] = DsEgrLtidSelectTcam_t;
        p_tcam_key_id[idx0++] = DsRouterMacTcamKey_t;
        p_tcam_key_id[idx0++] = ParserUdfCam_t;
        break;

    default:
       break;
    }

    *p_key_share_num = idx0;
    *p_ad_share_num  = idx1;
    return DRV_E_NONE;
}


/*
 * $)Ao?=o?=o?=o?=TCAM_ADo?=D4o?=P!o?=L6o?=o?=o?=,o?=o?=o?=o?=KEYo?=G2o?=M,o?=o?=,o?=o?=R*o?=o?=o?=o?=o?=o?=ADo?=D4o?=P!,o?=o?=o?=o?=o?=o?=F+o?=o?=o?=o?=o?=o?=
 */
static void
_drv_at_ftm_alloc_tcam_ad_map_to_new_word(uint8 lchip, uint32 tbl_id)
{

    switch (tbl_id)
    {
        case DsLpmTcamIpv4HalfKeyAd_t:
        case DsLpmTcamIpv4HalfKeyAdLookup1_t:
        case DsLpmTcamIpv4SaHalfKeyAdLookup1_t:
        case DsLpmTcamIpv4DaPubHalfKeyAdLookup1_t:
        case DsLpmTcamIpv4SaPubHalfKeyAdLookup1_t:
        case DsLpmTcamIpv4HalfKeyAdLookup2_t:
        case DsLpmTcamIpv4SaHalfKeyAdLookup2_t:
        case DsLpmTcamIpv4DaPubHalfKeyAdLookup2_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv4HalfKeyLookup1_t);
           break;

        case DsLpmTcamIpv6SaPubDoubleKey0Ad_t:
        case DsLpmTcamIpv6SaPubDoubleKey0AdLookup1_t:
        case DsLpmTcamIpv6DaPubDoubleKey0Ad_t:
        case DsLpmTcamIpv6DaPubDoubleKey0AdLookup1_t:
        case DsLpmTcamIpv6SaDoubleKey0Ad_t:
        case DsLpmTcamIpv6SaDoubleKey0AdLookup1_t:
        case DsLpmTcamIpv6DoubleKey0Ad_t:
        case DsLpmTcamIpv6DoubleKey0AdLookup1_t:
        case DsLpmTcamIpv6SaPubDoubleKey0AdLookup2_t:
        case DsLpmTcamIpv6DaPubDoubleKey0AdLookup2_t:
        case DsLpmTcamIpv6SaDoubleKey0AdLookup2_t:
        case DsLpmTcamIpv6DoubleKey0AdLookup2_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv6DoubleKey0Lookup1_t);
            break;

        case DsLpmTcamIpv6SingleKeyAd_t:
        case DsLpmTcamIpv6SaSingleKeyAd_t:
        case DsLpmTcamIpv6DaPubSingleKeyAd_t:
        case DsLpmTcamIpv6SaPubSingleKeyAd_t:
        case DsLpmTcamIpv4SaPubHalfKeyAdLookup2_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv6SingleKey_t);
            break;

        case DsNatTcamAd_t:
        case DsLpmTcamAd_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv4NatDoubleKey_t);
            break;
        case DsLpmTcamIpv4NatDoubleKeyAd_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv4NatDoubleKey_t);
            break;
        case DsLpmTcamIpv6NatDoubleKeyAd_t:
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size =
                TABLE_ENTRY_SIZE(lchip, DsLpmTcamIpv6DoubleKey1_t);
            break;

        default:
            break;
    }

}


tbls_ext_info_t*
_drv_at_ftm_build_tcam_tbl_info()
{
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    tcam_mem_ext_content_t* p_tcam_mem_ext_info = NULL;

    p_tbl_ext_info = mem_malloc(MEM_FTM_MODULE, sizeof(tbls_ext_info_t));
    if (NULL == p_tbl_ext_info)
    {
        return NULL;
    }

    sal_memset(p_tbl_ext_info, 0, sizeof(tbls_ext_info_t));

    p_tcam_mem_ext_info = mem_malloc(MEM_FTM_MODULE, sizeof(tcam_mem_ext_content_t));
    if (NULL == p_tcam_mem_ext_info)
    {
        mem_free(p_tbl_ext_info);
        return NULL;
    }

    sal_memset(p_tcam_mem_ext_info, 0, sizeof(tcam_mem_ext_content_t));
    p_tcam_mem_ext_info->hw_mask_base =  mem_malloc(MEM_FTM_MODULE, sizeof(addrs_t)*3);
    if (NULL == p_tcam_mem_ext_info->hw_mask_base )
    {
        mem_free(p_tcam_mem_ext_info);
        mem_free(p_tbl_ext_info);
        return NULL;
    }
    p_tbl_ext_info->ptr_ext_content = p_tcam_mem_ext_info;

    return p_tbl_ext_info;

}

static int32
_drv_at_ftm_alloc_tcam_key_share_tbl(uint8 lchip, uint8 tcam_key_type, tbls_id_t tbl_id)
{
    uint32 max_index_num = 0;
    uint32 mem_id = 0;
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    uint32  is_lpm = 0;
    int32   per_entry_bytes = 0;
    uint32  mem_entry      = 0;

    if(!TABLE_EXT_INFO_PTR(lchip, tbl_id))
    {
        p_tbl_ext_info = _drv_at_ftm_build_tcam_tbl_info();
        if (NULL == p_tbl_ext_info)
        {
            return DRV_E_NO_MEMORY;
        }
        TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;
    }
    else
    {
        max_index_num = TABLE_MAX_INDEX(lchip, tbl_id);
    }
    per_entry_bytes            = DRV_BYTES_PER_ENTRY;

    switch(tcam_key_type)
    {
        case DRV_FTM_TCAM_TYPE_IGS_LPM_ALL:
        case DRV_FTM_TCAM_TYPE_IGS_LPM0DA:
        case DRV_FTM_TCAM_TYPE_IGS_LPM0SA:
        case DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB:
        case DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_LPM;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_LPM;
            per_entry_bytes             = DRV_LPM_KEY_BYTES_PER_ENTRY;
            is_lpm                      = 1;
            if (DRV_FTM_KEY_MEM_BITMAP(DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB)[0] || DRV_FTM_KEY_MEM_BITMAP(DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB)[1])
            {
                TCAM_EXT_INFO_PTR(lchip, tbl_id)->lpm_type = (tcam_key_type == DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB)?1:2;
            }
            else if(DRV_FTM_KEY_MEM_BITMAP(DRV_FTM_TCAM_TYPE_IGS_LPM0SA)[0] || DRV_FTM_KEY_MEM_BITMAP(DRV_FTM_TCAM_TYPE_IGS_LPM0SA)[1])
            {
                TCAM_EXT_INFO_PTR(lchip, tbl_id)->lpm_type = (tcam_key_type != DRV_FTM_TCAM_TYPE_IGS_LPM0SA)?1:2;
            }
            break;

        case DRV_FTM_TCAM_TYPE_IGS_LPM1:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_LPM;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_NAT;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = 2;
            per_entry_bytes             = DRV_LPM_KEY_BYTES_PER_ENTRY;
            is_lpm                      = 1;
            break;

        case DRV_FTM_TCAM_TYPE_IGS_USERID0:
        case DRV_FTM_TCAM_TYPE_IGS_USERID1:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_SCL0;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_I_SCL0;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = tcam_key_type - DRV_FTM_TCAM_TYPE_IGS_USERID0;
            break;
        case DRV_FTM_TCAM_TYPE_IGS_USERID2:
        case DRV_FTM_TCAM_TYPE_IGS_USERID3:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_SCL1;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_I_SCL1;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = tcam_key_type - DRV_FTM_TCAM_TYPE_IGS_USERID2;
            break;

        case DRV_FTM_TCAM_TYPE_IGS_ACL0:
        case DRV_FTM_TCAM_TYPE_IGS_ACL1:
        case DRV_FTM_TCAM_TYPE_IGS_ACL2:
        case DRV_FTM_TCAM_TYPE_IGS_ACL3:
        case DRV_FTM_TCAM_TYPE_IGS_ACL4:
        case DRV_FTM_TCAM_TYPE_IGS_ACL5:
        case DRV_FTM_TCAM_TYPE_IGS_ACL6:
        case DRV_FTM_TCAM_TYPE_IGS_ACL7:
        case DRV_FTM_TCAM_TYPE_IGS_ACL8:
        case DRV_FTM_TCAM_TYPE_IGS_ACL9:
        case DRV_FTM_TCAM_TYPE_IGS_ACL10:
        case DRV_FTM_TCAM_TYPE_IGS_ACL11:
        case DRV_FTM_TCAM_TYPE_IGS_ACL12:
        case DRV_FTM_TCAM_TYPE_IGS_ACL13:
        case DRV_FTM_TCAM_TYPE_IGS_ACL14:
        case DRV_FTM_TCAM_TYPE_IGS_ACL15:
        case DRV_FTM_TCAM_TYPE_IGS_ACL16:
        case DRV_FTM_TCAM_TYPE_IGS_ACL17:
        case DRV_FTM_TCAM_TYPE_IGS_ACL18:
        case DRV_FTM_TCAM_TYPE_IGS_ACL19:
        case DRV_FTM_TCAM_TYPE_IGS_ACL20:
        case DRV_FTM_TCAM_TYPE_IGS_ACL21:
        case DRV_FTM_TCAM_TYPE_IGS_ACL22:
        case DRV_FTM_TCAM_TYPE_IGS_ACL23:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_ACL;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_I_ACL;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = tcam_key_type - DRV_FTM_TCAM_TYPE_IGS_ACL0;
            break;

        case DRV_FTM_TCAM_TYPE_EGS_ACL0:
        case DRV_FTM_TCAM_TYPE_EGS_ACL1:
        case DRV_FTM_TCAM_TYPE_EGS_ACL2:
        case DRV_FTM_TCAM_TYPE_EGS_ACL3:
        case DRV_FTM_TCAM_TYPE_EGS_ACL4:
        case DRV_FTM_TCAM_TYPE_EGS_ACL5:
        case DRV_FTM_TCAM_TYPE_EGS_ACL6:
        case DRV_FTM_TCAM_TYPE_EGS_ACL7:
        case DRV_FTM_TCAM_TYPE_EGS_ACL8:
        case DRV_FTM_TCAM_TYPE_EGS_ACL9:
        case DRV_FTM_TCAM_TYPE_EGS_ACL10:
        case DRV_FTM_TCAM_TYPE_EGS_ACL11:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_EGR_ACL;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_E_ACL;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = tcam_key_type - DRV_FTM_TCAM_TYPE_EGS_ACL0;
            break;

        case DRV_FTM_TCAM_TYPE_EGS_SCL0:
        case DRV_FTM_TCAM_TYPE_EGS_SCL1:
            TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM;
            TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_EGR_SCL;
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_E_SCL;
            TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0) = tcam_key_type - DRV_FTM_TCAM_TYPE_EGS_SCL0;
            break;

        default:
            break;
    }

    if (TABLE_ENTRY_SIZE(lchip, tbl_id) == 0)
    {
        DRV_FTM_DBG_DUMP("tbl_id:%d size is zero!!!\n", tbl_id);
        return DRV_E_NONE;
    }

    /*tcam io*/
    TABLE_IOCTL_TYPE(lchip, tbl_id) = DRV_TBL_TYPE_TCAM;

    TCAM_KEY_TYPE(lchip, tbl_id) = tcam_key_type;
    TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size = TABLE_ENTRY_SIZE(lchip, tbl_id);
    TCAM_BITMAP(lchip, tbl_id)[0] |= DRV_FTM_KEY_MEM_BITMAP(tcam_key_type)[0];
    TCAM_BITMAP(lchip, tbl_id)[1] |= DRV_FTM_KEY_MEM_BITMAP(tcam_key_type)[1];


    if (is_lpm)
    {
        for (mem_id = 0; mem_id < DRV_CONST(DRV_MAX_LPM_TCAM_NUM); mem_id++)
        {
            /* if share list is no info in the block ,continue */
            if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, (tbl_id)), mem_id))
            {
                continue;
            }

            mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_LPM_TCAM_KEY0+mem_id);
            TCAM_DATA_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_LPM_TCAM_KEY0+mem_id);
            TCAM_MASK_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_LPM_TCAM_KEY0+mem_id);

            TCAM_ENTRY_NUM(lchip, tbl_id, mem_id)      = mem_entry;
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->tcam_alloc_info.tcam_mem_entry_start_index[mem_id]    = max_index_num;

            /* lpm per 46bit $)Ao?=o?=, o?=o?=o??o?=o?=o?=V?/ (R;o?=o?=o?=o?=R*o?=o?=o?=o?=46bit) == o?=o?=o?=o?=o?=Y8o?=index */
            /* NAT /PBR 96bit $)Ao?=o?=, o?=o?=o??o?=o?=o?=V?/ (R;o?=o?=o?=o?=R*o?=o?=o?=o?=46bit) == o?=o?=o?=o?=o?=Y8o?=index */
            max_index_num += (mem_entry / (TABLE_ENTRY_SIZE(lchip, tbl_id) / per_entry_bytes));
            TCAM_END_INDEX(lchip, tbl_id, mem_id) = (max_index_num - 1);
        }
    }
    else
    {
        for (mem_id = 0; mem_id < DRV_CONST(DRV_MAX_NOR_TCAM_NUM); mem_id++)
        {
            if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, tbl_id), mem_id))
            {
                continue;
            }
            mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_TCAM_KEY0+mem_id);
            TCAM_DATA_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_TCAM_KEY0+mem_id);
            TCAM_MASK_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_TCAM_KEY0+mem_id);

            TCAM_ENTRY_NUM(lchip, tbl_id, mem_id)      =  mem_entry;
            TCAM_EXT_INFO_PTR(lchip, tbl_id)->tcam_alloc_info.tcam_mem_entry_start_index[mem_id]    = max_index_num;

            max_index_num += (mem_entry / (TABLE_ENTRY_SIZE(lchip, tbl_id) / per_entry_bytes));
            TCAM_END_INDEX(lchip, tbl_id, mem_id) = (max_index_num - 1);
        }
    }

    TABLE_EXT_INFO(lchip, tbl_id).entry = max_index_num;
    TABLE_INFO(lchip, tbl_id).entry = 0;

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_tcam_tbl_info_detail(uint8 lchip, char* P_tbl_name)
{
    uint8 index = 0;
    uint32 tcam_key_type = 0;
    uint32 tcam_key_id = MaxTblId_t;
    uint32 tcam_key_a[20] = {0};
    uint32 tcam_ad_a[20] = {0};
    uint8 key_share_num  = 0;
    uint8 ad_share_num  = 0;
    uint8 mem_idx = 0;
    uint8 mem_id = 0;
    //uint32 mem_entry = 0;
    uint32 tbl_id = 0;
    uint8 size_type = 0;

    DRV_INIT_CHECK(lchip);
    if (DRV_E_NONE != drv_usw_get_tbl_id_by_string(lchip, &tbl_id, (char*)P_tbl_name))
    {

        DRV_FTM_DBG_OUT("%% Not found %s\n", P_tbl_name);
        return DRV_E_INVALID_TBL;
    }

    for (tcam_key_type = DRV_FTM_TCAM_TYPE_IGS_ACL0; tcam_key_type < DRV_FTM_TCAM_TYPE_MAX; tcam_key_type++)
    {

        DRV_IF_ERROR_RETURN(_drv_at_ftm_get_tcam_info(lchip, tcam_key_type,
                                                          tcam_key_a,
                                                          tcam_ad_a,
                                                          &key_share_num,
                                                          &ad_share_num));

        if (0 == key_share_num || 0 == ad_share_num)
        {
            continue;
        }

        /*tcam key alloc*/
        for (index = 0; index < key_share_num; index++)
        {
            tcam_key_id = tcam_key_a[index];

            if (tcam_key_id >= MaxTblId_t)
            {
                return DRV_E_NONE;
            }

            if ( (NULL == TABLE_INFO_PTR(lchip, tcam_key_id)) || 0 == TABLE_FIELD_NUM(lchip, tcam_key_id))
            {
                continue;
            }

            if (tcam_key_id != tbl_id)
            {
                continue;
            }

            size_type = TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size / (DRV_LPM_KEY_BYTES_PER_ENTRY);
            if (size_type == 2)
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMSingle;
            }
            else if(size_type == 4)
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMDouble;
            }
            else
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMhalf;
            }

            for (mem_idx = DRV_FTM_LPM_TCAM_KEY0; mem_idx < DRV_FTM_LPM_TCAM_KEYM; mem_idx++)
            {
                mem_id = mem_idx - DRV_FTM_LPM_TCAM_KEY0;

                /* if share list is no info in the block ,continue */
                if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, (tcam_key_id)), mem_id))
                {
                    continue;
                }

                //mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_idx);

                DRV_FTM_DBG_OUT("%-30s :%s\n", "Tcam Table ID", TABLE_NAME(lchip, tcam_key_id));
                DRV_FTM_DBG_OUT("%-30s :%d\n", "Tcam Memory ID", mem_id);
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Memory max entry", TCAM_ENTRY_NUM(lchip, tcam_key_id, mem_id));
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table Start Idx In Mem", TCAM_START_INDEX(lchip, tcam_key_id, mem_id));
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table End Idx In Mem", TCAM_END_INDEX(lchip, tcam_key_id, mem_id));

                //DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Spec max entry num", g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][size_type]);
               // DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table Start Idx In Spec", g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][size_type]);
                DRV_FTM_DBG_OUT("\n");
            }
        }

        for (index = 0; index < ad_share_num; index++)
        {
            tcam_key_id = tcam_ad_a[index];

            if (tcam_key_id >= MaxTblId_t)
            {
                return DRV_E_NONE;
            }

            if ( (NULL == TABLE_INFO_PTR(lchip, tcam_key_id)) || 0 == TABLE_FIELD_NUM(lchip, tcam_key_id))
            {
                continue;
            }

            if (tcam_key_id != tbl_id)
            {
                continue;
            }

            size_type = TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size / (DRV_LPM_KEY_BYTES_PER_ENTRY);
            if (size_type == 2)
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMSingle;
            }
            else if(size_type == 4)
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMDouble;
            }
            else
            {
                size_type = DRV_FTM_TCAM_SIZE_LPMhalf;
            }

            for (mem_idx = DRV_FTM_LPM_TCAM_KEY0; mem_idx < DRV_FTM_LPM_TCAM_KEYM; mem_idx++)
            {
                mem_id = mem_idx - DRV_FTM_LPM_TCAM_KEY0;

                /* if share list is no info in the block ,continue */
                if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, (tcam_key_id)), mem_id))
                {
                    continue;
                }

                //mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_idx);

                DRV_FTM_DBG_OUT("%-30s :%s\n", "Tcam Table ID", TABLE_NAME(lchip, tcam_key_id));
                DRV_FTM_DBG_OUT("%-30s :%d\n", "Tcam Memory ID", mem_id);
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Memory max entry", TCAM_ENTRY_NUM(lchip, tcam_key_id, mem_id));
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table Start Idx In Mem", TCAM_START_INDEX(lchip, tcam_key_id, mem_id));
                DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table End Idx In Mem", TCAM_END_INDEX(lchip, tcam_key_id, mem_id));

                //DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Spec max entry num", g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][size_type]);
               // DRV_FTM_DBG_OUT("%-30s :0x%x\n", "Table Start Idx In Spec", g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][size_type]);
                DRV_FTM_DBG_OUT("\n");
            }
        }

    }

    return DRV_E_NONE;
}

static int32
__drv_at_ftm_alloc_tcam_ad_share_tbl(uint8 lchip, uint8 tcam_key_type, uint32 tbl_id)
{
    uint32 max_index_num = 0;
    int8 mem_id = 0;
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    bool is_lpm = 0;
    uint8 per_entry_bytes = 0;
    uint32 mem_entry = 0;
    uint8 i = 0;
    uint8 is_first = 0;

    if(!TABLE_EXT_INFO_PTR(lchip, tbl_id))
    {
        p_tbl_ext_info = _drv_at_ftm_build_tcam_tbl_info();
        if (NULL == p_tbl_ext_info)
        {
          return DRV_E_NO_MEMORY;
        }

        TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;
    }
    else
    {
        max_index_num = TABLE_MAX_INDEX(lchip, tbl_id);
    }
    switch(tcam_key_type)
    {
    case DRV_FTM_TCAM_TYPE_IGS_LPM_ALL:

    case DRV_FTM_TCAM_TYPE_IGS_LPM0DA:
    case DRV_FTM_TCAM_TYPE_IGS_LPM0SA:
    case DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB:
    case DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB:
    //case DRV_FTM_TCAM_TYPE_IGS_LPM0DA_V6_HALF:
    //case DRV_FTM_TCAM_TYPE_IGS_LPM0SA_V6_HALF:
   // case DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB_V6_HALF:
    //case DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB_V6_HALF:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_LPM;
        per_entry_bytes         = DRV_LPM_AD0_BYTE_PER_ENTRY;
        is_lpm                      = 1;
        break;
    case DRV_FTM_TCAM_TYPE_IGS_LPM1:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_LPM;
        if (DsNatTcamAd_t == tbl_id)
        {
            per_entry_bytes         = 4;
        }
        else
        {
            per_entry_bytes         = DRV_LPM_AD1_BYTE_PER_ENTRY;
        }
        is_lpm                      = 1;
        break;

    case DRV_FTM_TCAM_TYPE_IGS_USERID0:
    case DRV_FTM_TCAM_TYPE_IGS_USERID1:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_SCL0;
        break;
    case DRV_FTM_TCAM_TYPE_IGS_USERID2:
    case DRV_FTM_TCAM_TYPE_IGS_USERID3:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_SCL1;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_ACL0:
    case DRV_FTM_TCAM_TYPE_EGS_ACL1:
    case DRV_FTM_TCAM_TYPE_EGS_ACL2:
    case DRV_FTM_TCAM_TYPE_EGS_ACL3:
    case DRV_FTM_TCAM_TYPE_EGS_ACL4:
    case DRV_FTM_TCAM_TYPE_EGS_ACL5:
    case DRV_FTM_TCAM_TYPE_EGS_ACL6:
    case DRV_FTM_TCAM_TYPE_EGS_ACL7:
    case DRV_FTM_TCAM_TYPE_EGS_ACL8:
    case DRV_FTM_TCAM_TYPE_EGS_ACL9:
    case DRV_FTM_TCAM_TYPE_EGS_ACL10:
    case DRV_FTM_TCAM_TYPE_EGS_ACL11:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_EGR_ACL;
        break;

    case DRV_FTM_TCAM_TYPE_EGS_SCL0:
    case DRV_FTM_TCAM_TYPE_EGS_SCL1:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_EGR_SCL;
        break;

    default:
        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_TCAM_AD;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_IGR_ACL;
        break;
    }

    TCAM_KEY_TYPE(lchip, tbl_id) = tcam_key_type;
        TCAM_BITMAP(lchip, tbl_id)[0] |= DRV_FTM_KEY_MEM_BITMAP(tcam_key_type)[0];
        TCAM_BITMAP(lchip, tbl_id)[1] |= DRV_FTM_KEY_MEM_BITMAP(tcam_key_type)[1];

    if (is_lpm)
    {
        for (mem_id = 0; mem_id < DRV_CONST(DRV_MAX_LPM_TCAM_NUM); mem_id++)
        {
            /* if share list is no info in the block ,continue */
            if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, tbl_id), mem_id))
            {
                continue;
            }
            if (!is_first)
            {
                TABLE_EXT_INFO(lchip, tbl_id).addrs[0] = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_LPM_TCAM_AD0 + mem_id);
                is_first++;
            }
            mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_LPM_TCAM_AD0+mem_id);

            TCAM_DATA_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_LPM_TCAM_AD0+mem_id);
            TCAM_ENTRY_NUM(lchip, tbl_id, mem_id)      = mem_entry;
            TCAM_START_INDEX(lchip, tbl_id, mem_id) = max_index_num;
            /* 46Bit */
            max_index_num += (mem_entry / (TABLE_ENTRY_SIZE(lchip, tbl_id) / per_entry_bytes));
            TCAM_END_INDEX(lchip, tbl_id, mem_id) = (max_index_num - 1);


            TCAM_TABLE_START(lchip, tbl_id, i)  = TCAM_START_INDEX(lchip, tbl_id, mem_id);
            TCAM_TABLE_END(lchip, tbl_id, i)  = TCAM_END_INDEX(lchip, tbl_id, mem_id);
            TCAM_TABLE_BLK_ID(lchip, tbl_id, i) = mem_id;
            i++;

        }
    }
    else
    {
        if (TCAM_KEY_MODULE(lchip, tbl_id) == TCAM_MODULE_IGR_SCL0)
        {
            per_entry_bytes = 16;
        }
        else if (TCAM_KEY_MODULE(lchip, tbl_id) == TCAM_MODULE_IGR_SCL1)
        {
            per_entry_bytes = 16;
        }
        else if (TCAM_KEY_MODULE(lchip, tbl_id) == TCAM_MODULE_IGR_ACL)
        {
            per_entry_bytes = 16;
        }
        else if (TCAM_KEY_MODULE(lchip, tbl_id) == TCAM_MODULE_EGR_ACL)
        {
            per_entry_bytes = 20;
        }
        else if (TCAM_KEY_MODULE(lchip, tbl_id) == TCAM_MODULE_EGR_SCL)
        {
            per_entry_bytes = 12;
        }

        for (mem_id = 0; mem_id < DRV_CONST(DRV_MAX_NOR_TCAM_NUM); mem_id++)
        {
            /* if share list is no info in the block ,continue */
            if (!DRV_BMP_ISSET(TCAM_BITMAP(lchip, tbl_id), mem_id))
            {
                continue;
            }

            mem_entry = DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_TCAM_AD0+mem_id);
            TABLE_EXT_INFO(lchip, tbl_id).addrs[0] = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_TCAM_AD0 + mem_id);
            TCAM_DATA_BASE(lchip, tbl_id, mem_id, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_TCAM_AD0+mem_id);
            TCAM_ENTRY_NUM(lchip, tbl_id, mem_id)      = mem_entry;
            TCAM_START_INDEX(lchip, tbl_id, mem_id)    = max_index_num;

            max_index_num += (mem_entry / (TABLE_ENTRY_SIZE(lchip, tbl_id)/per_entry_bytes));
            TCAM_END_INDEX(lchip, tbl_id, mem_id) = (max_index_num - 1);


            TCAM_TABLE_START(lchip, tbl_id, i)  = TCAM_START_INDEX(lchip, tbl_id, mem_id);
            TCAM_TABLE_END(lchip, tbl_id, i)  = TCAM_END_INDEX(lchip, tbl_id, mem_id);
            TCAM_TABLE_BLK_ID(lchip, tbl_id, i) = mem_id;
            i++;

            DRV_FTM_DBG_DUMP("Ad TCAM_START_INDEX(lchip, %20s, %d) = %d\n", TABLE_NAME(lchip, tbl_id), mem_id,  TCAM_START_INDEX(lchip, tbl_id, mem_id));
            DRV_FTM_DBG_DUMP("Ad TCAM_END_INDEX(lchip, %20s, %d) = %d\n", TABLE_NAME(lchip, tbl_id), mem_id, TCAM_END_INDEX(lchip, tbl_id, mem_id));
        }
    }

    TCAM_TABLE_BLK_NUM(lchip, tbl_id) = i;
    TABLE_EXT_INFO(lchip, tbl_id).entry = max_index_num;
    TABLE_INFO(lchip, tbl_id).entry = 0;
    _drv_at_ftm_alloc_tcam_ad_map_to_new_word(lchip, tbl_id);

    DRV_FTM_DBG_DUMP("Ad TCAM_BITMAP(lchip, %20s) = %d\n", TABLE_NAME(lchip, tbl_id), TCAM_BITMAP(lchip, tbl_id));
    DRV_FTM_DBG_DUMP("Ad TABLE_MAX_INDEX(lchip, %20s) = %d\n", TABLE_NAME(lchip, tbl_id), TABLE_MAX_INDEX(lchip, tbl_id));
    DRV_FTM_DBG_DUMP("----------------------------------------\n");

    return DRV_E_NONE;

}

static int32
_drv_at_ftm_alloc_tcam(uint8 lchip)
{
    uint8  index = 0;
    uint32 tcam_key_type = 0;
    uint32 tcam_key_id = MaxTblId_t;
    uint32 tcam_ad_tbl = MaxTblId_t;
    uint32 tcam_key_a[30] = {0};
    uint32 tcam_ad_a[30] = {0};
    uint8 key_share_num  = 0;
    uint8 ad_share_num  = 0;

    for (tcam_key_type = DRV_FTM_TCAM_TYPE_IGS_ACL0; tcam_key_type < DRV_FTM_TCAM_TYPE_MAX; tcam_key_type++)
    {
        DRV_IF_ERROR_RETURN(_drv_at_ftm_get_tcam_info(lchip,
                                                          tcam_key_type,
                                                          tcam_key_a,
                                                          tcam_ad_a,
                                                          &key_share_num,
                                                          &ad_share_num));

        if (0 == key_share_num || 0 == ad_share_num)
        {
            continue;
        }

        /*tcam key alloc*/
        for (index = 0; index < key_share_num; index++)
        {
            tcam_key_id = tcam_key_a[index];

            if (tcam_key_id >= MaxTblId_t)
            {
                DRV_FTM_DBG_DUMP("unexpect tbl id:%d\r\n", tcam_key_id);
                return DRV_E_INVAILD_TYPE;
            }

            if ( (NULL == TABLE_INFO_PTR(lchip, tcam_key_id)) || 0 == TABLE_FIELD_NUM(lchip, tcam_key_id))
            {
                continue;
            }
            DRV_IF_ERROR_RETURN(_drv_at_ftm_alloc_tcam_key_share_tbl(lchip, tcam_key_type, tcam_key_id));
        }

        /*tcam ad alloc*/
        for (index = 0; index < ad_share_num; index++)
        {
            tcam_ad_tbl = tcam_ad_a[index];

            if (tcam_ad_tbl >= MaxTblId_t)
            {
                DRV_FTM_DBG_DUMP("unexpect tbl id:%d\r\n", tcam_ad_tbl);
                return DRV_E_INVAILD_TYPE;
            }

            if ((NULL == TABLE_INFO_PTR(lchip, tcam_ad_tbl)) || 0 == TABLE_FIELD_NUM(lchip, tcam_ad_tbl))
            {
                continue;
            }
            DRV_IF_ERROR_RETURN(__drv_at_ftm_alloc_tcam_ad_share_tbl(lchip, tcam_key_type, tcam_ad_tbl));
        }

    }

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_alloc_static(uint8 lchip)
{
    uint8 index = 0;
    uint32 tcam_key_type = 0;
    uint32 tbl_id = MaxTblId_t;
    uint32 tcam_key_a[20] = {0};
    uint32 tcam_ad_a[20] = {0};
    uint8 key_share_num  = 0;
    uint8 ad_share_num  = 0;
    tbls_ext_info_t* p_tbl_ext_info = NULL;
    tcam_key_type = DRV_FTM_TCAM_TYPE_STATIC_TCAM;

    DRV_IF_ERROR_RETURN(_drv_at_ftm_get_tcam_info(lchip,tcam_key_type,
                                              tcam_key_a,
                                              tcam_ad_a,
                                              &key_share_num,
                                              &ad_share_num));

   /*tcam key alloc*/
    for (index = 0; index < key_share_num; index++)
    {
        tbl_id = tcam_key_a[index];

        if (tbl_id >= MaxTblId_t)
        {
            DRV_FTM_DBG_DUMP("unexpect tbl id:%d\r\n", tbl_id);
            return DRV_E_INVAILD_TYPE;
        }


        if ( (NULL == TABLE_INFO_PTR(lchip, tbl_id)) || 0 == TABLE_FIELD_NUM(lchip, tbl_id))
        {
             continue;
        }

        p_tbl_ext_info = _drv_at_ftm_build_tcam_tbl_info();
        if (NULL == p_tbl_ext_info)
        {
            return DRV_E_NO_MEMORY;
        }
        TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;

        TABLE_EXT_INFO_TYPE(lchip, tbl_id) = DRV_TABLE_TYPE_STATIC_TCAM_KEY;
        TCAM_KEY_MODULE(lchip, tbl_id) = TCAM_MODULE_NONE;
        TCAM_KEY_TYPE(lchip, tbl_id) = tcam_key_type;

        /*tcam io*/
        TABLE_IOCTL_TYPE(lchip, tbl_id) = DRV_TBL_TYPE_TCAM;

        TCAM_EXT_INFO_PTR(lchip, tbl_id)->key_size = TABLE_ENTRY_SIZE(lchip, tbl_id);/* table key size are in bytes */
        TCAM_BITMAP(lchip, tbl_id)[0] = 0;
        TCAM_BITMAP(lchip, tbl_id)[1] = 0;

        if (tbl_id == DsCategoryIdPairTcamKey_t)
        {
            TCAM_DATA_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_CID_TCAM);
            TCAM_MASK_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_CID_TCAM);
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_CID;
        }
        else if (tbl_id == DsLtidSelectTcam_t)
        {
            TCAM_DATA_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_SEL_TCAM);
            TCAM_MASK_BASE(lchip, tbl_id, 0, 0) =  DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_SEL_TCAM);
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_I_LTID;
        }
        else if (tbl_id == DsEgrLtidSelectTcam_t)
        {
            TCAM_DATA_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_SEL_TCAM_EGR);
            TCAM_MASK_BASE(lchip, tbl_id, 0, 0) =  DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_SEL_TCAM_EGR);
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_E_LTID;
        }
        else if (tbl_id == DsRouterMacTcamKey_t)
        {
            TCAM_DATA_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_RMAC_TCAM);
            TCAM_MASK_BASE(lchip, tbl_id, 0, 0) =  DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_RMAC_TCAM);
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_VMAC;
        }
        else if (tbl_id == ParserUdfCam_t)
        {
            TCAM_DATA_BASE(lchip, tbl_id, 0, 0) = DRV_FTM_MEM_HW_DATA_BASE(DRV_FTM_UDF_TCAM);
            TCAM_MASK_BASE(lchip, tbl_id, 0, 0) =  DRV_FTM_MEM_HW_MASK_BASE(DRV_FTM_UDF_TCAM);
            TCAM_KEY_DRV_TYPE(lchip, tbl_id) = DRV_IO_TCAM_TYPE_UDF;
        }

        TCAM_ENTRY_NUM(lchip, tbl_id, 0) = TABLE_MAX_INDEX(lchip, tbl_id);
        TCAM_TABLE_SW_BASE(lchip, tbl_id, 0) = 0;
        TCAM_EXT_INFO_PTR(lchip, tbl_id)->tcam_alloc_info.tcam_mem_entry_start_index[0]= 0;
        TCAM_END_INDEX(lchip, tbl_id, 0) = TABLE_MAX_INDEX(lchip, tbl_id) - 1;
    }

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_cam_by_tbl_id(uint8 lchip, uint32 tbl_id, uint8* cam_type, uint8* cam_num)
{
    uint8 type = DRV_FTM_CAM_TYPE_INVALID;

    switch(tbl_id)
    {
    case DsFibHost0MacHashKey_t:
        type = DRV_FTM_CAM_TYPE_FIB_MAC;
        *cam_num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM);
        break;

    case DsFibHost0FcoeHashKey_t:
    case DsFibHost0Ipv4HashKey_t:
    case DsFibHost0Ipv6McastHashKey_t:
    case DsFibHost0Ipv6UcastHashKey_t:
    case DsFibHost0MacIpv4McastHashKey_t:
    case DsFibHost0MacIpv6McastHashKey_t:
    case DsFibHost0TrillHashKey_t:
        type = DRV_FTM_CAM_TYPE_FIB_HOST0;
        *cam_num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM);
        break;

    case DsFibHost1FcoeRpfHashKey_t:
    case DsFibHost1Ipv4McastHashKey_t:
    case DsFibHost1Ipv4NatDaPortHashKey_t:
    case DsFibHost1Ipv4NatSaPortHashKey_t:
    case DsFibHost1Ipv6McastHashKey_t:
    case DsFibHost1Ipv6NatDaPortHashKey_t:
    case DsFibHost1Ipv6NatSaPortHashKey_t:
    case DsFibHost1MacIpv4McastHashKey_t:
    case DsFibHost1MacIpv6McastHashKey_t:
    case DsFibHost1TrillMcastVlanHashKey_t:
        type = DRV_FTM_CAM_TYPE_FIB_HOST1;
        *cam_num = DRV_CONST(DRV_FIB_HOST1_CAM_NUM);
        break;

    case DsOamEthHashKey_t:
    case DsOamBfdHashKey_t:
    case DsOamMplsLabelHashKey_t:
    case DsOamMplsSectionHashKey_t:
        type = DRV_FTM_CAM_TYPE_XC;
        *cam_num = DRV_CONST(DRV_OAM_HASH_CAM_NUM);
        break;


    case DsEthOamRmepRmepHashKey_t:
        type = DRV_FTM_CAM_TYPE_RMEP;
        *cam_num = DRV_CONST(DRV_RMEP_HASH_CAM_NUM);
        break;

    case DsEgressScl0CvlanCosPortHashKey_t:
    case DsEgressScl0CvlanPortHashKey_t:
    case DsEgressScl0DoubleVlanPortHashKey_t:
    case DsEgressScl0PortCrossHashKey_t:
    case DsEgressScl0PortHashKey_t:
    case DsEgressScl0PortVlanCrossHashKey_t:
    case DsEgressScl0SvlanCosPortHashKey_t:
    case DsEgressScl0SvlanPortHashKey_t:
    case DsEgressScl0SvlanPortMacHashKey_t:
    case DsEgressScl0FidDvpGroupHashKey_t:
    case DsEgressScl0MetadataDvpGroupHashKey_t:
    case DsEgressScl0XHashKey_t:
        type = DRV_FTM_CAM_TYPE_EGR_SCL;
        *cam_num = 0;
        break;

    case DsEgressScl1CvlanCosPortHashKey_t:
    case DsEgressScl1CvlanPortHashKey_t:
    case DsEgressScl1DoubleVlanPortHashKey_t:
    case DsEgressScl1PortCrossHashKey_t:
    case DsEgressScl1PortHashKey_t:
    case DsEgressScl1PortVlanCrossHashKey_t:
    case DsEgressScl1SvlanCosPortHashKey_t:
    case DsEgressScl1SvlanPortHashKey_t:
    case DsEgressScl1SvlanPortMacHashKey_t:
    case DsEgressScl1FidDvpGroupHashKey_t:
    case DsEgressScl1MetadataDvpGroupHashKey_t:
    case DsEgressScl1XHashKey_t:
        type = DRV_FTM_CAM_TYPE_EGR_SCL1;
        *cam_num = 0;
        break;

    case DsFlowL2HashKey_t:
    case DsFlowL2L3HashKey_t:
    case DsFlowL3Ipv4HashKey_t:
    case DsFlowL3Ipv6HashKey_t:
    case DsFlowL3MplsHashKey_t:
    case DsFlowFlexHashKey_t:
    case DsFlowNshForwardHashKey_t:
    case DsFlowXKeyDoubleHashKey_t:
    case DsFlowXKeyQuadHashKey_t:
        type = DRV_FTM_CAM_TYPE_FLOW;
        *cam_num = DRV_CONST(DRV_FLOW_HASH_CAM_NUM);
        break;

    case DsUserIdCvlanCosPortHashKey_t:
    case DsUserIdCvlanPortHashKey_t:
    case DsUserIdDoubleVlanPortHashKey_t:
    case DsUserIdEcidNameSpaceHashKey_t:
    case DsUserIdIngEcidNameSpaceHashKey_t:
    case DsUserIdIpv4PortHashKey_t:
    case DsUserIdIpv4SaHashKey_t:
    case DsUserIdIpv6PortHashKey_t:
    case DsUserIdIpv6SaHashKey_t:
    case DsUserIdIpv6DaHashKey_t:
    case DsUserIdMacHashKey_t:
    case DsUserIdMacPortHashKey_t:
    case DsUserIdPortHashKey_t:
    case DsUserIdSclFlowL2HashKey_t:
    case DsUserIdSclFlowL2UDFHashKey_t:
    case DsUserIdSclFlowL3UDFHashKey_t:
    case DsUserIdSvlanCosPortHashKey_t:
    case DsUserIdSvlanHashKey_t:
    case DsUserIdSvlanMacSaHashKey_t:
    case DsUserIdSvlanPortHashKey_t:
    case DsUserId0VlanPortDscpHashKey_t:
    case DsUserIdTunnelIpv4DaHashKey_t:
    case DsUserIdTunnelIpv4GreKeyHashKey_t:
    case DsUserIdTunnelIpv4HashKey_t:
    case DsUserIdTunnelIpv4McNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv4McVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv4NvgreMode1HashKey_t:
    case DsUserIdTunnelIpv4RpfHashKey_t:
    case DsUserIdTunnelIpv4UcNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv4UcNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv4UcVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv4UcVxlanMode1HashKey_t:
    case DsUserIdTunnelIpv4UdpHashKey_t:
    case DsUserIdTunnelIpv4VxlanMode1HashKey_t:
    case DsUserIdTunnelIpv6DaHashKey_t:
    case DsUserIdTunnelIpv6GreKeyHashKey_t:
    case DsUserIdTunnelIpv6HashKey_t:
    case DsUserIdTunnelIpv6UdpHashKey_t:
    case DsUserIdTunnelIpv6McNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv6McNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv6McVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv6McVxlanMode1HashKey_t:
    case DsUserIdTunnelIpv6UcNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv6UcNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv6UcVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv6UcVxlanMode1HashKey_t:
    case DsUserIdTunnelTrillMcAdjHashKey_t:
    case DsUserIdTunnelTrillMcDecapHashKey_t:
    case DsUserIdTunnelTrillMcRpfHashKey_t:
    case DsUserIdTunnelTrillUcDecapHashKey_t:
    case DsUserIdTunnelTrillUcRpfHashKey_t:
    case DsUserId0TunnelIpv4CloudSecHashKey_t:
    case DsUserId0TunnelIpv6CloudSecHashKey_t:
    case DsUserId0XKeySingleHashKey_t:
    case DsUserId0XKeyDoubleHashKey_t:
    case DsUserId0XKeyQuadHashKey_t:
    case DsUserIdNshHashKey_t:
        type = DRV_FTM_CAM_TYPE_IGR_SCL0;
        *cam_num = 0;
        break;

    case DsUserId1CvlanCosPortHashKey_t:
    case DsUserId1CvlanPortHashKey_t:
    case DsUserId1DoubleVlanPortHashKey_t:
    case DsUserId1EcidNameSpaceHashKey_t:
    case DsUserId1IngEcidNameSpaceHashKey_t:
    case DsUserId1Ipv4PortHashKey_t:
    case DsUserId1Ipv4SaHashKey_t:
    case DsUserId1Ipv6PortHashKey_t:
    case DsUserId1Ipv6SaHashKey_t:
    case DsUserId1Ipv6DaHashKey_t:
    case DsUserId1MacHashKey_t:
    case DsUserId1MacPortHashKey_t:
    case DsUserId1PortHashKey_t:
    case DsUserId1SclFlowL2HashKey_t:
    case DsUserId1SclFlowL2UDFHashKey_t:
    case DsUserId1SclFlowL3UDFHashKey_t:
    case DsUserId1SvlanCosPortHashKey_t:
    case DsUserId1SvlanHashKey_t:
    case DsUserId1SvlanMacSaHashKey_t:
    case DsUserId1SvlanPortHashKey_t:
    case DsUserId1VlanPortDscpHashKey_t:
    case DsUserId1TunnelIpv4DaHashKey_t:
    case DsUserId1TunnelIpv4GreKeyHashKey_t:
    case DsUserId1TunnelIpv4HashKey_t:
    case DsUserId1TunnelIpv4McNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv4McVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv4NvgreMode1HashKey_t:
    case DsUserId1TunnelIpv4RpfHashKey_t:
    case DsUserId1TunnelIpv4UcNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv4UcNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv4UcVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv4UcVxlanMode1HashKey_t:
    case DsUserId1TunnelIpv4UdpHashKey_t:
    case DsUserId1TunnelIpv4VxlanMode1HashKey_t:
    case DsUserId1TunnelIpv6DaHashKey_t:
    case DsUserId1TunnelIpv6GreKeyHashKey_t:
    case DsUserId1TunnelIpv6HashKey_t:
    case DsUserId1TunnelIpv6UdpHashKey_t:
    case DsUserId1TunnelIpv6McNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv6McNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv6McVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv6McVxlanMode1HashKey_t:
    case DsUserId1TunnelIpv6UcNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv6UcNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv6UcVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv6UcVxlanMode1HashKey_t:
    case DsUserId1TunnelTrillMcAdjHashKey_t:
    case DsUserId1TunnelTrillMcDecapHashKey_t:
    case DsUserId1TunnelTrillMcRpfHashKey_t:
    case DsUserId1TunnelTrillUcDecapHashKey_t:
    case DsUserId1TunnelTrillUcRpfHashKey_t:
    case DsUserId1TunnelIpv4CloudSecHashKey_t:
    case DsUserId1TunnelIpv6CloudSecHashKey_t:
    case DsUserId1XKeySingleHashKey_t:
    case DsUserId1XKeyDoubleHashKey_t:
    case DsUserId1XKeyQuadHashKey_t:
    case DsUserId1NshHashKey_t:
        type = DRV_FTM_CAM_TYPE_IGR_SCL1;
        *cam_num = 0;
        break;

    case DsMplsLabelHashKey_t:
        type = DRV_FTM_CAM_TYPE_MPLS_HASH;
        *cam_num = DRV_CONST(DRV_MPLS_HASH_CAM_NUM);
        break;

    case DsXSecRxL2BasicHashKey_t:
    case DsXSecRxL2MacsecHashKey_t:
    case DsXSecRxL3L4V4HashKey_t:
    case DsXSecRxL3L4V6HashKey_t:
    case DsXSecRxSpiHashKey_t:
        type = DRV_FTM_CAM_TYPE_XSEC_RX;
        *cam_num = DRV_CONST(DRV_DOT1AE_HASH_CAM_NUM);
        break;

    case DsXSecTxL2BasicHashKey_t:
    case DsXSecTxL3L4V4HashKey_t:
    case DsXSecTxL3L4V6HashKey_t:
    case DsXSecTxSpiHashKey_t:
        type = DRV_FTM_CAM_TYPE_XSEC_TX;
        *cam_num = DRV_CONST(DRV_DOT1AE_HASH_CAM_NUM);
        break;

    default:
        return DRV_E_INVAILD_TYPE;
    }

    *cam_type = type;

    return DRV_E_NONE;
}


static int32
_drv_at_ftm_set_profile(uint8 lchip, drv_ftm_profile_info_t *profile_info)
{
    uint8 profile_index    = 0;

    profile_index = profile_info->profile_type;
    switch (profile_index)
    {
    case 0:
        DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_default(lchip));
        break;

    case 12:
        DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile_user_define(lchip, profile_info));
        break;

    default:
        return DRV_E_NONE;
    }

    return DRV_E_NONE;

}

#define DRV_DT2_FTM_D(sram_tbl,name)
#define DRV_DT2_FTM_F(sram_id,ctc_poly,drv_poly,couple_ctc_poly,couple_drv_poly)
#define DRV_DT2_FTM_DD(sram_tbl,name,ref_sram_tbl)
#define DRV_TM_FTM_D(sram_tbl,name)
#define DRV_TM_FTM_F(sram_id,ctc_poly,drv_poly,couple_ctc_poly,couple_drv_poly)
#define DRV_TM_FTM_DD(sram_tbl,name,ref_sram_tbl)
#define DRV_TMM_FTM_D(sram_tbl,name)
#define DRV_TMM_FTM_F(sram_id,ctc_poly,drv_poly,couple_ctc_poly,couple_drv_poly)
#define DRV_TMM_FTM_DD(sram_tbl,name,ref_sram_tbl)

/*poly map of sram table*/
#define DRV_AT_FTM_DD(sram_tbl,name,ref_sram_tbl)
#define DRV_AT_FTM_D(sram_tbl,name)     \
    };\
    drv_ftm_tbl_poly_t drv_at_ftm_ ## name ## _poly[] = {
#define DRV_AT_FTM_F(sram_id,ctc_poly,drv_poly,couple_ctc_poly,couple_drv_poly) \
    {sram_id,{{ctc_poly,drv_poly},{couple_ctc_poly,couple_drv_poly}}},

drv_ftm_tbl_poly_t drv_at_ftm_head_poly[] = {
    {DRV_FTM_EDRAM_MAX,{{0,0},{0,0}}},
    #include "usw/include/drv_ftm_poly_map.h"
};

static int32
_drv_at_ftm_init_hash_poly(uint8 lchip)
{
#undef DRV_AT_FTM_D
#undef DRV_AT_FTM_F
#undef DRV_AT_FTM_DD
#define DRV_AT_FTM_F(sram_id,ctc_poly,drv_poly,couple_ctc_poly,couple_drv_poly)
#define DRV_AT_FTM_DD(sram_tbl,name,ref_sram_tbl)   \
    sal_memcpy(&DRV_FTM_TBL_HASH_POLY(sram_tbl), &DRV_FTM_TBL_HASH_POLY(ref_sram_tbl), sizeof(drv_ftm_hash_poly_t));
#define DRV_AT_FTM_D(sram_tbl,name)     \
    DRV_FTM_TBL_HASH_POLY(sram_tbl).sram_poly = drv_at_ftm_ ## name ## _poly;\
    DRV_FTM_TBL_HASH_POLY(sram_tbl).sram_num = sizeof(drv_at_ftm_ ## name ## _poly)/sizeof(drv_ftm_tbl_poly_t);

    #include "usw/include/drv_ftm_poly_map.h"

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_init(uint8 lchip, drv_ftm_profile_info_t *profile_info)
{
    uint8 loop =0;
    if (NULL != g_at_ftm_master[lchip])
    {
        return DRV_E_NONE;
    }

	if (lchip != drv_vchip_get_pp_base(lchip))
	{
		g_at_ftm_master[lchip] = g_at_ftm_master[drv_vchip_get_pp_base(lchip)];
		return DRV_E_NONE;
	}

    g_at_ftm_master[lchip] = mem_malloc(MEM_FTM_MODULE, sizeof(g_ftm_master_t));
    if (NULL == g_at_ftm_master[lchip])
    {
        return DRV_E_NO_MEMORY;
    }
    sal_memset(g_at_ftm_master[lchip], 0, sizeof(g_ftm_master_t));
    g_at_ftm_master[lchip]->p_sram_tbl_info =
        mem_malloc(MEM_FTM_MODULE, sizeof(drv_ftm_sram_tbl_info_t) * DRV_FTM_SRAM_TBL_MAX);
    if (NULL == g_at_ftm_master[lchip]->p_sram_tbl_info)
    {
        mem_free(g_at_ftm_master[lchip]);
        return DRV_E_NO_MEMORY;
    }

    sal_memset(g_at_ftm_master[lchip]->p_sram_tbl_info, 0, sizeof(drv_ftm_sram_tbl_info_t) * DRV_FTM_SRAM_TBL_MAX);

    g_at_ftm_master[lchip]->p_tcam_key_info =
        mem_malloc(MEM_FTM_MODULE, sizeof(drv_ftm_tcam_key_info_t) * DRV_FTM_TCAM_TYPE_MAX);
    if (NULL == g_at_ftm_master[lchip]->p_tcam_key_info)
    {
        mem_free(g_at_ftm_master[lchip]->p_sram_tbl_info);
        mem_free(g_at_ftm_master[lchip]);
        return DRV_E_NO_MEMORY;
    }

    sal_memset(g_at_ftm_master[lchip]->p_tcam_key_info, 0, sizeof(drv_ftm_tcam_key_info_t) * DRV_FTM_TCAM_TYPE_MAX);

    g_at_ftm_master[lchip]->lpm_model = profile_info->lpm_mode;
    g_at_ftm_master[lchip]->napt_enable= profile_info->napt_enable;

    g_at_ftm_master[lchip]->mpls_enable = profile_info->mpls_en?1:0;
    g_at_ftm_master[lchip]->scl_mode = profile_info->scl_mode;

    for (loop = lchip + 1; loop < drv_vchip_get_pp_num(lchip); loop++)
    {
        g_at_ftm_master[loop] = g_at_ftm_master[drv_vchip_get_pp_base(lchip)];
    }
#if (SDK_WORK_PLATFORM == 1)
extern uint8 g_drv_vchip_mode;
    if (g_drv_vchip_mode)
    {
        for (loop = lchip + drv_vchip_get_pp_num(lchip); loop < lchip + drv_vchip_get_pp_num(lchip)*2; loop++)
        {
            g_at_ftm_master[loop] = g_at_ftm_master[drv_vchip_get_pp_base(lchip)];
        }
    }
#endif
    return DRV_E_NONE;
}

static int32
_drv_at_tcam_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 single_key_bmp = 0;
    uint8  field_idx = 0;
    uint32 mode = 0;
    uint32 sel = 0;
    uint32 value = 0;
    LpmTcamCtl_m lpmtcam;
    uint32 ipv6_lookup64_prefix_field[] = {LpmTcamCtl_tcamGroupConfig_0_ipv6Lookup64Prefix_f, LpmTcamCtl_tcamGroupConfig_1_ipv6Lookup64Prefix_f,
                                           LpmTcamCtl_tcamGroupConfig_2_ipv6Lookup64Prefix_f, LpmTcamCtl_tcamGroupConfig_3_ipv6Lookup64Prefix_f,
                                           LpmTcamCtl_tcamGroupConfig_4_ipv6Lookup64Prefix_f, LpmTcamCtl_tcamGroupConfig_5_ipv6Lookup64Prefix_f};

    if (DRV_FROM_TMM(lchip)
       && (LPM_MODEL_PUBLIC_IPDA == g_at_ftm_master[lchip]->lpm_model
       || LPM_MODEL_PUBLIC_IPDA_IPSA_HALF == g_at_ftm_master[lchip]->lpm_model
       || LPM_MODEL_PUBLIC_IPDA_IPSA_FULL == g_at_ftm_master[lchip]->lpm_model))
    {
        DRV_FTM_DBG_OUT("Invalid lpm tcam profile:%u\n", g_at_ftm_master[lchip]->lpm_model);
        return DRV_E_INVALID_PARAMETER;
    }

    cmd = DRV_IOW(FibNeoLpmCtl_t, FibNeoLpmCtl_neoLpmMode_f);
    if (g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PRIVATE_IPDA
        || g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PRIVATE_IPDA_IPSA_FULL
        || g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF)
    {
        /* fullSizeMode = 1 */
    }
    else if (g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF)
    {
        sel = 2;
    }
    else if (g_at_ftm_master[lchip]->lpm_model == LPM_MODEL_PRIVATE_IPDA_IPSA_HALF)
    {
        sel = 1;
    }
    DRV_IF_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &sel));

    if (DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_LPM_LKP_KEY0), DRV_FTM_SRAM2)
        || DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_LPM_LKP_KEY0), DRV_FTM_SRAM3))
    {
        sel = 1;
        cmd = DRV_IOW(FibNeoLpmCtl_t, FibNeoLpmCtl_multiLevelEn_f);
        DRV_IF_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &sel));
    }

    cmd = DRV_IOR(LpmTcamCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lpmtcam));

    SetLpmTcamCtl(V, privatePublicLookupMode_f, &lpmtcam, g_at_ftm_master[lchip]->lpm_model);
    SetLpmTcamCtl(V, natTcamLookupEn_f, &lpmtcam, g_at_ftm_master[lchip]->nat_pbr_enable);
    #if 0
    SetLpmTcamCtl(V, lpmTcamLookup2Division_f, &lpmtcam, 0);
    #endif
    /*enable single key, single & v4 share the same ram*/
    if (g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1]!= 0)
    {
        single_key_bmp = g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][1] | g_at_ftm_master[lchip]->lpm_tcam_init_bmp[0][2];
        for (field_idx=0; field_idx < 6; field_idx++)
        {
            value = DRV_IS_BIT_SET(single_key_bmp, field_idx) ? 1 : 0;
            DRV_IOW_FIELD(lchip, LpmTcamCtl_t, ipv6_lookup64_prefix_field[field_idx], &value, &lpmtcam);
        }
    }
    if (g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1]!= 0)
    {
        single_key_bmp = g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][1] | g_at_ftm_master[lchip]->lpm_tcam_init_bmp[1][2];
        for (field_idx=0; field_idx < 6; field_idx++)
        {
            value = DRV_IS_BIT_SET(single_key_bmp, field_idx) ? 1 : 0;
            DRV_IOW_FIELD(lchip, LpmTcamCtl_t, ipv6_lookup64_prefix_field[field_idx], &value, &lpmtcam);
        }
    }

    cmd = DRV_IOW(LpmTcamCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lpmtcam));

    cmd = DRV_IOW(NeoLpmCtl_t, NeoLpmCtl_fullSizeMode_f);
    /*full size, performace within 1 time*/
    if (LPM_MODEL_PRIVATE_IPDA == g_at_ftm_master[lchip]->lpm_model
       || LPM_MODEL_PRIVATE_IPDA_IPSA_FULL == g_at_ftm_master[lchip]->lpm_model
       || LPM_MODEL_PUBLIC_IPDA_PRIVATE_IPDA_HALF == g_at_ftm_master[lchip]->lpm_model)
    {
        mode = 1;
    }
            /*half size, 2 times lookup, performace within 2 times*/
    else if (LPM_MODEL_PRIVATE_IPDA_IPSA_HALF == g_at_ftm_master[lchip]->lpm_model
            /*half size, 4 times lookup, performace within 2 times*/
            || LPM_MODEL_PUBLIC_IPDA_IPSA_PRIVATE_IPDA_IPSA_HALF == g_at_ftm_master[lchip]->lpm_model)
    {
        mode = 0;
    }
    DRV_IF_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &mode));
    return DRV_E_NONE;
}


static int32
_drv_at_dynamic_cam_init_antflow(uint32 lchip)
{
    uint8 unit                    = DRV_FTM_UNIT_1K + 3; /* antflow once access 8k table */
    uint32 cmd                = 0;
    uint8 i = 0;
    uint32 bitmap = 0;
    uint32 bitmap2 = 0;
    uint32 min_idx[2] = {0};
    uint32 max_idx[2] = {0};
    DynamicKeyCpuAntFlowIndexCam_m cpu_cam;
    DynamicKeyDsAgingAntFlowIndexCam_m aging_cam;
    sal_memset(&cpu_cam, 0, sizeof(cpu_cam));
    sal_memset(&aging_cam, 0, sizeof(aging_cam));

    bitmap = DRV_FTM_TBL_BASE_BITMAP(DRV_FTM_SRAM_TBL_ANT_FLOW);
    bitmap2 = DRV_FTM_TBL_BASE_BITMAP(DRV_FTM_SRAM_TBL_ANT_FLOW2);
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &aging_cam, DRV_IS_BIT_SET(bitmap | bitmap2, 0));
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &aging_cam, DRV_IS_BIT_SET(bitmap | bitmap2, 1));

    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowCamEnable0_f, &cpu_cam, DRV_IS_BIT_SET(bitmap | bitmap2, 0));
    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowCamEnable1_f, &cpu_cam, DRV_IS_BIT_SET(bitmap | bitmap2, 1));

    for (i = 0; i < 2; i++)
    {
        if (!DRV_IS_BIT_SET(bitmap | bitmap2, i))
        { continue;}
        min_idx[i] = DRV_FTM_TBL_BASE_MIN(DRV_FTM_SRAM_TBL_ANT_FLOW, i) + DRV_FTM_TBL_BASE_MIN(DRV_FTM_SRAM_TBL_ANT_FLOW2, i);
        min_idx[i] >>= unit;
        max_idx[i] = DRV_FTM_TBL_BASE_MAX(DRV_FTM_SRAM_TBL_ANT_FLOW, i) + DRV_FTM_TBL_BASE_MAX(DRV_FTM_SRAM_TBL_ANT_FLOW2, i);
        max_idx[i] >>= unit;
    }
    if (bitmap == 3 || bitmap2 == 3)
    {
        /* do nothing */
    }
    else if ((bitmap | bitmap2) == 3)
    {
        min_idx[1] = max_idx[0] + 1;
        max_idx[1] += min_idx[1];
    }
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowMinIndex0_f, &aging_cam, min_idx[0]);
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowMinIndex1_f, &aging_cam, min_idx[1]);
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowMaxIndex0_f, &aging_cam, max_idx[0]);
    SetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowMaxIndex1_f, &aging_cam, max_idx[1]);
    cmd = DRV_IOW(DynamicKeyDsAgingAntFlowIndexCam_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &aging_cam));

    /*when CPU access the antFlow table, RTL use the high bit of the table address as memory id, so the min index and the max index is fixed.
      which memory to choose is determined by camEnable*/
    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowMinIndex0_f, &cpu_cam, 0);
    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowMinIndex1_f, &cpu_cam, 32);
    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowMaxIndex0_f, &cpu_cam, 31);
    SetDynamicKeyCpuAntFlowIndexCam(V, cpuAntFlowMaxIndex1_f, &cpu_cam, 63);
    cmd = DRV_IOW(DynamicKeyCpuAntFlowIndexCam_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cpu_cam));
    return DRV_E_NONE;
}

static int32
_drv_at_dynamic_cam_init(uint32 lchip)
{

    uint32 cmd                = 0;
    uint32 field_id_en[DRV_FTM_MAX_MEM_NUM]        = {0};
    uint32 field_id_base[DRV_FTM_MAX_MEM_NUM]      = {0};
    uint32 field_id_max_index[DRV_FTM_MAX_MEM_NUM] = {0};
    uint32 field_id_min_index[DRV_FTM_MAX_MEM_NUM] = {0};

    uint32 ds[32] = {0};
    uint8 i = 0;
    uint8 idx = 0;
    uint32 field_val          = 0;
    uint32 tbl_id             = 0;
    uint32 tbl_id_array[5]   = {0};

    //uint32 sum               = 0;
    uint32 bitmap            = 0;
    uint8 cam_type            = 0;
    uint8 sram_type           = 0;
    uint8 unit                    = DRV_FTM_UNIT_8K;
    drv_ftm_sram_id_info_t* p_sram_node = NULL;

    for (cam_type = 0; cam_type < DRV_FTM_DYN_CAM_TYPE_MAX; cam_type++)
    {
        idx = 0;

        switch (cam_type)
        {
            case DRV_FTM_DYN_AD_DS_FLOW:
                sram_type = DRV_FTM_SRAM_TBL_FLOW_AD;
                tbl_id_array[idx++] = DynamicAdDsFlowIndexCam_t;

                field_id_en[0] = DynamicAdDsFlowIndexCam_dsFlowCamEnable0_f;
                field_id_en[1] = DynamicAdDsFlowIndexCam_dsFlowCamEnable1_f;
                field_id_en[2] = DynamicAdDsFlowIndexCam_dsFlowCamEnable2_f;
                field_id_en[3] = DynamicAdDsFlowIndexCam_dsFlowCamEnable3_f;
                field_id_base[0] = DynamicAdDsFlowIndexCam_dsFlowBaseAddr0_f;
                field_id_base[1] = DynamicAdDsFlowIndexCam_dsFlowBaseAddr1_f;
                field_id_base[2] = DynamicAdDsFlowIndexCam_dsFlowBaseAddr2_f;
                field_id_base[3] = DynamicAdDsFlowIndexCam_dsFlowBaseAddr3_f;
                field_id_min_index[0] = DynamicAdDsFlowIndexCam_dsFlowMinIndex0_f;
                field_id_min_index[1] = DynamicAdDsFlowIndexCam_dsFlowMinIndex1_f;
                field_id_min_index[2] = DynamicAdDsFlowIndexCam_dsFlowMinIndex2_f;
                field_id_min_index[3] = DynamicAdDsFlowIndexCam_dsFlowMinIndex3_f;
                field_id_max_index[0] = DynamicAdDsFlowIndexCam_dsFlowMaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsFlowIndexCam_dsFlowMaxIndex1_f;
                field_id_max_index[2] = DynamicAdDsFlowIndexCam_dsFlowMaxIndex2_f;
                field_id_max_index[3] = DynamicAdDsFlowIndexCam_dsFlowMaxIndex3_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_AD_DS_IP:
                sram_type = DRV_FTM_SRAM_TBL_DSIP_AD;
                tbl_id_array[idx++] = DynamicAdDsIpIndexCam_t;

                field_id_en[0] = DynamicAdDsIpIndexCam_dsIpCamEnable0_f;
                field_id_en[1] = DynamicAdDsIpIndexCam_dsIpCamEnable1_f;
                field_id_en[2] = DynamicAdDsIpIndexCam_dsIpCamEnable2_f;
                field_id_en[3] = DynamicAdDsIpIndexCam_dsIpCamEnable3_f;
                field_id_base[0] = DynamicAdDsIpIndexCam_dsIpBaseAddr0_f;
                field_id_base[1] = DynamicAdDsIpIndexCam_dsIpBaseAddr1_f;
                field_id_base[2] = DynamicAdDsIpIndexCam_dsIpBaseAddr2_f;
                field_id_base[3] = DynamicAdDsIpIndexCam_dsIpBaseAddr3_f;
                field_id_min_index[0] = DynamicAdDsIpIndexCam_dsIpMinIndex0_f;
                field_id_min_index[1] = DynamicAdDsIpIndexCam_dsIpMinIndex1_f;
                field_id_min_index[2] = DynamicAdDsIpIndexCam_dsIpMinIndex2_f;
                field_id_min_index[3] = DynamicAdDsIpIndexCam_dsIpMinIndex3_f;
                field_id_max_index[0] = DynamicAdDsIpIndexCam_dsIpMaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsIpIndexCam_dsIpMaxIndex1_f;
                field_id_max_index[2] = DynamicAdDsIpIndexCam_dsIpMaxIndex2_f;
                field_id_max_index[3] = DynamicAdDsIpIndexCam_dsIpMaxIndex3_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_AD_DS_MAC:
                sram_type = DRV_FTM_SRAM_TBL_DSMAC_AD;
                tbl_id_array[idx++] = DynamicAdDsMacIndexCam_t;

                field_id_en[0] = DynamicAdDsMacIndexCam_dsMacCamEnable0_f;
                field_id_en[1] = DynamicAdDsMacIndexCam_dsMacCamEnable1_f;
                field_id_en[2] = DynamicAdDsMacIndexCam_dsMacCamEnable2_f;
                field_id_en[3] = DynamicAdDsMacIndexCam_dsMacCamEnable3_f;
                field_id_base[0] = DynamicAdDsMacIndexCam_dsMacBaseAddr0_f;
                field_id_base[1] = DynamicAdDsMacIndexCam_dsMacBaseAddr1_f;
                field_id_base[2] = DynamicAdDsMacIndexCam_dsMacBaseAddr2_f;
                field_id_base[3] = DynamicAdDsMacIndexCam_dsMacBaseAddr3_f;
                field_id_min_index[0] = DynamicAdDsMacIndexCam_dsMacMinIndex0_f;
                field_id_min_index[1] = DynamicAdDsMacIndexCam_dsMacMinIndex1_f;
                field_id_min_index[2] = DynamicAdDsMacIndexCam_dsMacMinIndex2_f;
                field_id_min_index[3] = DynamicAdDsMacIndexCam_dsMacMinIndex3_f;
                field_id_max_index[0] = DynamicAdDsMacIndexCam_dsMacMaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsMacIndexCam_dsMacMaxIndex1_f;
                field_id_max_index[2] = DynamicAdDsMacIndexCam_dsMacMaxIndex2_f;
                field_id_max_index[3] = DynamicAdDsMacIndexCam_dsMacMaxIndex3_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_AD_DS_MPLS:
                sram_type = DRV_FTM_SRAM_TBL_MPLS_HASH_AD;
                tbl_id_array[idx++] = DynamicAdDsMplsIndexCam_t;

                field_id_en[0] = DynamicAdDsMplsIndexCam_dsMplsCamEnable0_f;
                field_id_en[1] = DynamicAdDsMplsIndexCam_dsMplsCamEnable1_f;
                field_id_base[0] = DynamicAdDsMplsIndexCam_dsMplsBaseAddr0_f;
                field_id_base[1] = DynamicAdDsMplsIndexCam_dsMplsBaseAddr1_f;
                field_id_min_index[0] = DynamicAdDsMplsIndexCam_dsMplsMinIndex0_f;
                field_id_min_index[1] = DynamicAdDsMplsIndexCam_dsMplsMinIndex1_f;
                field_id_max_index[0] = DynamicAdDsMplsIndexCam_dsMplsMaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsMplsIndexCam_dsMplsMaxIndex1_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_AD_DS_SCL0:
                sram_type = DRV_FTM_SRAM_TBL_USERID_AD;
                tbl_id_array[idx++] = DynamicAdDsScl0IndexCam_t;

                field_id_en[0] = DynamicAdDsScl0IndexCam_dsScl0CamEnable0_f;
                field_id_en[1] = DynamicAdDsScl0IndexCam_dsScl0CamEnable1_f;
                field_id_en[2] = DynamicAdDsScl0IndexCam_dsScl0CamEnable2_f;
                field_id_en[3] = DynamicAdDsScl0IndexCam_dsScl0CamEnable3_f;
                field_id_en[4] = DynamicAdDsScl0IndexCam_dsScl0CamEnable4_f;
                field_id_base[0] = DynamicAdDsScl0IndexCam_dsScl0BaseAddr0_f;
                field_id_base[1] = DynamicAdDsScl0IndexCam_dsScl0BaseAddr1_f;
                field_id_base[2] = DynamicAdDsScl0IndexCam_dsScl0BaseAddr2_f;
                field_id_base[3] = DynamicAdDsScl0IndexCam_dsScl0BaseAddr3_f;
                field_id_base[4] = DynamicAdDsScl0IndexCam_dsScl0BaseAddr4_f;
                field_id_min_index[0] = DynamicAdDsScl0IndexCam_dsScl0MinIndex0_f;
                field_id_min_index[1] = DynamicAdDsScl0IndexCam_dsScl0MinIndex1_f;
                field_id_min_index[2] = DynamicAdDsScl0IndexCam_dsScl0MinIndex2_f;
                field_id_min_index[3] = DynamicAdDsScl0IndexCam_dsScl0MinIndex3_f;
                field_id_min_index[4] = DynamicAdDsScl0IndexCam_dsScl0MinIndex4_f;
                field_id_max_index[0] = DynamicAdDsScl0IndexCam_dsScl0MaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsScl0IndexCam_dsScl0MaxIndex1_f;
                field_id_max_index[2] = DynamicAdDsScl0IndexCam_dsScl0MaxIndex2_f;
                field_id_max_index[3] = DynamicAdDsScl0IndexCam_dsScl0MaxIndex3_f;
                field_id_max_index[4] = DynamicAdDsScl0IndexCam_dsScl0MaxIndex4_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_AD_DS_SCL1:
                sram_type = DRV_FTM_SRAM_TBL_USERID_AD1;
                tbl_id_array[idx++] = DynamicAdDsScl1IndexCam_t;

                field_id_en[0] = DynamicAdDsScl1IndexCam_dsScl1CamEnable0_f;
                field_id_en[1] = DynamicAdDsScl1IndexCam_dsScl1CamEnable1_f;
                field_id_base[0] = DynamicAdDsScl1IndexCam_dsScl1BaseAddr0_f;
                field_id_base[1] = DynamicAdDsScl1IndexCam_dsScl1BaseAddr1_f;
                field_id_min_index[0] = DynamicAdDsScl1IndexCam_dsScl1MinIndex0_f;
                field_id_min_index[1] = DynamicAdDsScl1IndexCam_dsScl1MinIndex1_f;
                field_id_max_index[0] = DynamicAdDsScl1IndexCam_dsScl1MaxIndex0_f;
                field_id_max_index[1] = DynamicAdDsScl1IndexCam_dsScl1MaxIndex1_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_FWD_POST:
                sram_type = DRV_FTM_SRAM_TBL_FWD2;
                tbl_id_array[idx++] = DynamicEditDsFwdPostIndexCam_t;

                field_id_en[0] = DynamicEditDsFwdPostIndexCam_dsFwdPostCamEnable0_f;
                field_id_en[1] = DynamicEditDsFwdPostIndexCam_dsFwdPostCamEnable1_f;
                field_id_en[2] = DynamicEditDsFwdPostIndexCam_dsFwdPostCamEnable2_f;
                field_id_base[0] = DynamicEditDsFwdPostIndexCam_dsFwdPostBaseAddr0_f;
                field_id_base[1] = DynamicEditDsFwdPostIndexCam_dsFwdPostBaseAddr1_f;
                field_id_base[2] = DynamicEditDsFwdPostIndexCam_dsFwdPostBaseAddr2_f;
                field_id_min_index[0] = DynamicEditDsFwdPostIndexCam_dsFwdPostMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsFwdPostIndexCam_dsFwdPostMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsFwdPostIndexCam_dsFwdPostMinIndex2_f;
                field_id_max_index[0] = DynamicEditDsFwdPostIndexCam_dsFwdPostMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsFwdPostIndexCam_dsFwdPostMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsFwdPostIndexCam_dsFwdPostMaxIndex2_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DSFWD_PRE:
                sram_type = DRV_FTM_SRAM_TBL_FWD;
                tbl_id_array[idx++] = DynamicEditDsFwdPreIndexCam_t;

                field_id_en[0] = DynamicEditDsFwdPreIndexCam_dsFwdPreCamEnable0_f;
                field_id_en[1] = DynamicEditDsFwdPreIndexCam_dsFwdPreCamEnable1_f;
                field_id_en[2] = DynamicEditDsFwdPreIndexCam_dsFwdPreCamEnable2_f;
                field_id_base[0] = DynamicEditDsFwdPreIndexCam_dsFwdPreBaseAddr0_f;
                field_id_base[1] = DynamicEditDsFwdPreIndexCam_dsFwdPreBaseAddr1_f;
                field_id_base[2] = DynamicEditDsFwdPreIndexCam_dsFwdPreBaseAddr2_f;
                field_id_min_index[0] = DynamicEditDsFwdPreIndexCam_dsFwdPreMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsFwdPreIndexCam_dsFwdPreMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsFwdPreIndexCam_dsFwdPreMinIndex2_f;
                field_id_max_index[0] = DynamicEditDsFwdPreIndexCam_dsFwdPreMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsFwdPreIndexCam_dsFwdPreMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsFwdPreIndexCam_dsFwdPreMaxIndex2_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_INNER_EDIT:
                sram_type = DRV_FTM_SRAM_TBL_EDIT;
                tbl_id_array[idx++] = DynamicEditDsInnerEditIndexCam_t;

                field_id_en[0] = DynamicEditDsInnerEditIndexCam_dsInnerEditCamEnable0_f;
                field_id_en[1] = DynamicEditDsInnerEditIndexCam_dsInnerEditCamEnable1_f;
                field_id_en[2] = DynamicEditDsInnerEditIndexCam_dsInnerEditCamEnable2_f;
                field_id_en[3] = DynamicEditDsInnerEditIndexCam_dsInnerEditCamEnable3_f;
                field_id_en[4] = DynamicEditDsInnerEditIndexCam_dsInnerEditCamEnable4_f;
                field_id_base[0] = DynamicEditDsInnerEditIndexCam_dsInnerEditBaseAddr0_f;
                field_id_base[1] = DynamicEditDsInnerEditIndexCam_dsInnerEditBaseAddr1_f;
                field_id_base[2] = DynamicEditDsInnerEditIndexCam_dsInnerEditBaseAddr2_f;
                field_id_base[3] = DynamicEditDsInnerEditIndexCam_dsInnerEditBaseAddr3_f;
                field_id_base[4] = DynamicEditDsInnerEditIndexCam_dsInnerEditBaseAddr4_f;
                field_id_min_index[0] = DynamicEditDsInnerEditIndexCam_dsInnerEditMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsInnerEditIndexCam_dsInnerEditMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsInnerEditIndexCam_dsInnerEditMinIndex2_f;
                field_id_min_index[3] = DynamicEditDsInnerEditIndexCam_dsInnerEditMinIndex3_f;
                field_id_min_index[4] = DynamicEditDsInnerEditIndexCam_dsInnerEditMinIndex4_f;
                field_id_max_index[0] = DynamicEditDsInnerEditIndexCam_dsInnerEditMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsInnerEditIndexCam_dsInnerEditMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsInnerEditIndexCam_dsInnerEditMaxIndex2_f;
                field_id_max_index[3] = DynamicEditDsInnerEditIndexCam_dsInnerEditMaxIndex3_f;
                field_id_max_index[4] = DynamicEditDsInnerEditIndexCam_dsInnerEditMaxIndex4_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_NEXT_HOP:
                sram_type = DRV_FTM_SRAM_TBL_NEXTHOP;
                tbl_id_array[idx++] = DynamicEditDsNextHopIndexCam_t;

                field_id_en[0] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable0_f;
                field_id_en[1] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable1_f;
                field_id_en[2] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable2_f;
                field_id_en[3] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable3_f;
                field_id_en[4] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable4_f;
                field_id_en[5] = DynamicEditDsNextHopIndexCam_dsNextHopCamEnable5_f;
                field_id_base[0] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr0_f;
                field_id_base[1] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr1_f;
                field_id_base[2] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr2_f;
                field_id_base[3] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr3_f;
                field_id_base[4] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr4_f;
                field_id_base[5] = DynamicEditDsNextHopIndexCam_dsNextHopBaseAddr5_f;
                field_id_min_index[0] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex2_f;
                field_id_min_index[3] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex3_f;
                field_id_min_index[4] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex4_f;
                field_id_min_index[5] = DynamicEditDsNextHopIndexCam_dsNextHopMinIndex5_f;
                field_id_max_index[0] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex2_f;
                field_id_max_index[3] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex3_f;
                field_id_max_index[4] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex4_f;
                field_id_max_index[5] = DynamicEditDsNextHopIndexCam_dsNextHopMaxIndex5_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_NEXT_HOP_MAP:
                sram_type = DRV_FTM_SRAM_TBL_NHOFST_MAP;
                tbl_id_array[idx++] = DynamicEditDsNextHopMapIndexCam_t;

                field_id_en[0] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapCamEnable0_f;
                field_id_en[1] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapCamEnable1_f;
                field_id_en[2] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapCamEnable2_f;
                field_id_base[0] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapBaseAddr0_f;
                field_id_base[1] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapBaseAddr1_f;
                field_id_base[2] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapBaseAddr2_f;
                field_id_min_index[0] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMinIndex2_f;
                field_id_max_index[0] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsNextHopMapIndexCam_dsNextHopMapMaxIndex2_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_OUTER_EDIT:
                sram_type = DRV_FTM_SRAM_TBL_EDIT_OUTER;
                tbl_id_array[idx++] = DynamicEditDsOuterEditIndexCam_t;

                field_id_en[0] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable0_f;
                field_id_en[1] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable1_f;
                field_id_en[2] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable2_f;
                field_id_en[3] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable3_f;
                field_id_en[4] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable4_f;
                field_id_en[5] = DynamicEditDsOuterEditIndexCam_dsOuterEditCamEnable5_f;
                field_id_base[0] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr0_f;
                field_id_base[1] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr1_f;
                field_id_base[2] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr2_f;
                field_id_base[3] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr3_f;
                field_id_base[4] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr4_f;
                field_id_base[5] = DynamicEditDsOuterEditIndexCam_dsOuterEditBaseAddr5_f;
                field_id_min_index[0] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex2_f;
                field_id_min_index[3] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex3_f;
                field_id_min_index[4] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex4_f;
                field_id_min_index[5] = DynamicEditDsOuterEditIndexCam_dsOuterEditMinIndex5_f;
                field_id_max_index[0] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex2_f;
                field_id_max_index[3] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex3_f;
                field_id_max_index[4] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex4_f;
                field_id_max_index[5] = DynamicEditDsOuterEditIndexCam_dsOuterEditMaxIndex5_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_EDIT_DS_X_EDIT:
                sram_type = DRV_FTM_SRAM_TBL_EDIT2;
                tbl_id_array[idx++] = DynamicEditDsXEditIndexCam_t;

                field_id_en[0] = DynamicEditDsXEditIndexCam_dsXEditCamEnable0_f;
                field_id_en[1] = DynamicEditDsXEditIndexCam_dsXEditCamEnable1_f;
                field_id_en[2] = DynamicEditDsXEditIndexCam_dsXEditCamEnable2_f;
                field_id_en[3] = DynamicEditDsXEditIndexCam_dsXEditCamEnable3_f;
                field_id_en[4] = DynamicEditDsXEditIndexCam_dsXEditCamEnable4_f;
                field_id_en[5] = DynamicEditDsXEditIndexCam_dsXEditCamEnable5_f;
                field_id_en[6] = DynamicEditDsXEditIndexCam_dsXEditCamEnable6_f;
                field_id_base[0] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr0_f;
                field_id_base[1] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr1_f;
                field_id_base[2] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr2_f;
                field_id_base[3] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr3_f;
                field_id_base[4] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr4_f;
                field_id_base[5] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr5_f;
                field_id_base[6] = DynamicEditDsXEditIndexCam_dsXEditBaseAddr6_f;
                field_id_min_index[0] = DynamicEditDsXEditIndexCam_dsXEditMinIndex0_f;
                field_id_min_index[1] = DynamicEditDsXEditIndexCam_dsXEditMinIndex1_f;
                field_id_min_index[2] = DynamicEditDsXEditIndexCam_dsXEditMinIndex2_f;
                field_id_min_index[3] = DynamicEditDsXEditIndexCam_dsXEditMinIndex3_f;
                field_id_min_index[4] = DynamicEditDsXEditIndexCam_dsXEditMinIndex4_f;
                field_id_min_index[5] = DynamicEditDsXEditIndexCam_dsXEditMinIndex5_f;
                field_id_min_index[6] = DynamicEditDsXEditIndexCam_dsXEditMinIndex6_f;
                field_id_max_index[0] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex0_f;
                field_id_max_index[1] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex1_f;
                field_id_max_index[2] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex2_f;
                field_id_max_index[3] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex3_f;
                field_id_max_index[4] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex4_f;
                field_id_max_index[5] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex5_f;
                field_id_max_index[6] = DynamicEditDsXEditIndexCam_dsXEditMaxIndex6_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_KEY_IPE_ANT_FLOW:
                sram_type = DRV_FTM_SRAM_TBL_ANT_FLOW2;
                tbl_id_array[idx++] = DynamicKeyIpeAntFlowIndexCam_t;

                field_id_en[0] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowCamEnable0_f;
                field_id_en[1] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowCamEnable1_f;
                field_id_base[0] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowBaseAddr0_f;
                field_id_base[1] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowBaseAddr1_f;
                field_id_min_index[0] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowMinIndex0_f;
                field_id_min_index[1] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowMinIndex1_f;
                field_id_max_index[0] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowMaxIndex0_f;
                field_id_max_index[1] = DynamicKeyIpeAntFlowIndexCam_ipeAntFlowMaxIndex1_f;

                unit = DRV_FTM_UNIT_1K+2; /*antflow 8k unit*/
                break;
            case DRV_FTM_DYN_KEY_LINK_AGG_ANT_FLOW:
                sram_type = DRV_FTM_SRAM_TBL_ANT_FLOW;
                tbl_id_array[idx++] = DynamicKeyLinkAggAntFlowIndexCam_t;

                field_id_en[0] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowCamEnable0_f;
                field_id_en[1] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowCamEnable1_f;
                field_id_base[0] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowBaseAddr0_f;
                field_id_base[1] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowBaseAddr1_f;
                field_id_min_index[0] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowMinIndex0_f;
                field_id_min_index[1] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowMinIndex1_f;
                field_id_max_index[0] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowMaxIndex0_f;
                field_id_max_index[1] = DynamicKeyLinkAggAntFlowIndexCam_linkAggAntFlowMaxIndex1_f;

                unit = DRV_FTM_UNIT_1K+2; /*antflow 8k unit*/
                break;
            case DRV_FTM_DYN_KEY_MAC_KEY:
                sram_type = DRV_FTM_SRAM_TBL_MAC_HASH_KEY;
                tbl_id_array[idx++] = DynamicKeyMacKeyIndexCam_t;

                field_id_en[0] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable0_f;
                field_id_en[1] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable1_f;
                field_id_en[2] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable2_f;
                field_id_en[3] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable3_f;
                field_id_en[4] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable4_f;
                field_id_en[5] = DynamicKeyMacKeyIndexCam_host0KeyCamEnable5_f;
                field_id_base[0] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr0_f;
                field_id_base[1] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr1_f;
                field_id_base[2] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr2_f;
                field_id_base[3] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr3_f;
                field_id_base[4] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr4_f;
                field_id_base[5] = DynamicKeyMacKeyIndexCam_host0KeyBaseAddr5_f;
                field_id_min_index[0] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex0_f;
                field_id_min_index[1] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex1_f;
                field_id_min_index[2] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex2_f;
                field_id_min_index[3] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex3_f;
                field_id_min_index[4] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex4_f;
                field_id_min_index[5] = DynamicKeyMacKeyIndexCam_host0KeyMinIndex5_f;
                field_id_max_index[0] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex0_f;
                field_id_max_index[1] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex1_f;
                field_id_max_index[2] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex2_f;
                field_id_max_index[3] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex3_f;
                field_id_max_index[4] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex4_f;
                field_id_max_index[5] = DynamicKeyMacKeyIndexCam_host0KeyMaxIndex5_f;

                unit = DRV_FTM_UNIT_1K;
                break;
            case DRV_FTM_DYN_KEY_SHARE_MET:
                sram_type = DRV_FTM_SRAM_TBL_MET2;
                tbl_id_array[idx++] = DynamicKeyShareMetIndexCam_t;

                field_id_en[0] = DynamicKeyShareMetIndexCam_shareMetCamEnable0_f;
                field_id_en[1] = DynamicKeyShareMetIndexCam_shareMetCamEnable1_f;
                field_id_en[2] = DynamicKeyShareMetIndexCam_shareMetCamEnable2_f;
                field_id_en[3] = DynamicKeyShareMetIndexCam_shareMetCamEnable3_f;
                field_id_base[0] = DynamicKeyShareMetIndexCam_shareMetBaseAddr0_f;
                field_id_base[1] = DynamicKeyShareMetIndexCam_shareMetBaseAddr1_f;
                field_id_base[2] = DynamicKeyShareMetIndexCam_shareMetBaseAddr2_f;
                field_id_base[3] = DynamicKeyShareMetIndexCam_shareMetBaseAddr3_f;
                field_id_min_index[0] = DynamicKeyShareMetIndexCam_shareMetMinIndex0_f;
                field_id_min_index[1] = DynamicKeyShareMetIndexCam_shareMetMinIndex1_f;
                field_id_min_index[2] = DynamicKeyShareMetIndexCam_shareMetMinIndex2_f;
                field_id_min_index[3] = DynamicKeyShareMetIndexCam_shareMetMinIndex3_f;
                field_id_max_index[0] = DynamicKeyShareMetIndexCam_shareMetMaxIndex0_f;
                field_id_max_index[1] = DynamicKeyShareMetIndexCam_shareMetMaxIndex1_f;
                field_id_max_index[2] = DynamicKeyShareMetIndexCam_shareMetMaxIndex2_f;
                field_id_max_index[3] = DynamicKeyShareMetIndexCam_shareMetMaxIndex3_f;

                unit = DRV_FTM_UNIT_1K;
                break;

        default:
           continue;
        }

        bitmap = DRV_FTM_TBL_BASE_BITMAP(sram_type);
        tbl_id = tbl_id_array[0];

        sal_memset(ds, 0, sizeof(ds));
        tbl_id = tbl_id_array[0];
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        for (i = 0; i < DRV_FTM_MAX_MEM_NUM; i++)
        {
            if (!DRV_IS_BIT_SET(bitmap, i))
            {
                continue;
            }

            p_sram_node = _drv_at_ftm_get_sram_db_node(lchip, sram_type, i);
            if (!p_sram_node)
            {
                continue;
            }
            if (field_id_en[i] != DRV_FTM_FLD_INVALID)
            {
                /*write ds cam enable value*/
                field_val = 1;
                DRV_SET_FIELD_V(lchip, tbl_id, field_id_en[i],   ds,   field_val );
            }

            if (field_id_base[i] != DRV_FTM_FLD_INVALID)
            {
                /*write ds cam base value*/
                field_val = p_sram_node->mem_offset;
                field_val = (field_val >> unit);
                DRV_SET_FIELD_V(lchip, tbl_id, field_id_base[i],   ds,   field_val );
            }

            if (field_id_min_index[i] != DRV_FTM_FLD_INVALID)
            {
                /*write ds cam min value*/
                field_val = p_sram_node->min_index;
                field_val = (field_val >> unit);
                DRV_SET_FIELD_V(lchip, tbl_id, field_id_min_index[i], ds, field_val );
            }

            if (field_id_max_index[i] != DRV_FTM_FLD_INVALID)
            {
                /*write ds cam max value*/
                field_val = p_sram_node->max_index;
                field_val = (field_val >> unit);
                DRV_SET_FIELD_V(lchip, tbl_id, field_id_max_index[i], ds, field_val );
            }

        }

        for (i = 0; i < idx; i++)
        {
            tbl_id = tbl_id_array[i];
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }

    }
    DRV_IF_ERROR_RETURN(_drv_at_dynamic_cam_init_antflow(lchip));
    return DRV_E_NONE;
}



STATIC int32
_drv_at_dynamic_arb_init(uint32 lchip)
{
/*AT_TODO*/
    tbls_id_t table_id = MaxTblId_t;
    uint32 cmd = 0;
    uint32 ds[MAX_ENTRY_WORD] = {0};
    uint32 bit_set = 0;
    uint32 is_couple = 0;
    uint32 one = 1, two = 2;

#define SRAM_Process(I, SRAM_TYPE, SRAM) \
{\
    bit_set = DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(SRAM_TYPE), SRAM);\
    is_couple = DRV_FTM_TBL_COUPLE_MODE(SRAM_TYPE);\
    if(bit_set && is_couple)\
    {\
        DRV_IOW_FIELD(lchip, table_id, ArbTblFldCouple(I, Couple), &one, ds);\
        DRV_IOW_FIELD(lchip, table_id, ArbTblFldCoupleMode(I), &one, ds);\
    }\
}

#define SRAM_Process2(I, SRAM_TYPE, SRAM) \
{\
    bit_set = DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(SRAM_TYPE), SRAM);\
    is_couple = DRV_FTM_TBL_COUPLE_MODE(SRAM_TYPE);\
    if(bit_set && is_couple)\
    {\
        DRV_IOW_FIELD(lchip, table_id, ArbTblFldCouple(I, Couple), &one, ds);\
        DRV_IOW_FIELD(lchip, table_id, ArbTblFldCoupleMode(I), &two, ds);\
    }\
}

#define ArbTable_Init(I) \
{\
    sal_memset(ds, 0, sizeof(ds));\
    table_id = ArbTable(I);\
}

#define ArbTable_Write \
{\
    cmd = DRV_IOW(table_id, DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
}

#define ArbTable(i) DynamicKeyShareRam##i##Ctl_t
#define ArbTblFld(i, fld) DynamicKeyShareRam##i##Ctl_shareKeyRam##i##fld##_f
#define ArbTblFldCouple(i, fld) DynamicKeyShareRam##i##Ctl_shareKeyRam##i##Local##fld##_f
#define ArbTblFldCoupleMode(i) DynamicKeyShareRam##i##Ctl_shareKeyRam##i##CoupleMode_f

    /* Fib Share SRAM 0 */
    ArbTable_Init(0);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM0);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM0);
    ArbTable_Write;

    /* Fib Share SRAM 1 */
    ArbTable_Init(1);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM1);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM1);
    ArbTable_Write;

    /* Fib Share SRAM 2 */
    ArbTable_Init(2);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM2);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM2);
    SRAM_Process2(2, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM2);
    SRAM_Process2(2, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM2);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM2);
    ArbTable_Write;

    /* Fib Share SRAM 3 */
    ArbTable_Init(3);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM3);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM3);
    SRAM_Process2(3, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM3);
    SRAM_Process2(3, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM3);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM3);
    ArbTable_Write;

    /* Fib Share SRAM 4 */
    ArbTable_Init(4);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM4);
    SRAM_Process2(4, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM4);
    SRAM_Process2(4, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM4);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM4);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_MET2, DRV_FTM_SRAM4);
    ArbTable_Write;

    /* Fib Share SRAM 5 */
    ArbTable_Init(5);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_MAC_HASH_KEY, DRV_FTM_SRAM5);
    SRAM_Process2(5, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM5);
    SRAM_Process2(5, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM5);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM5);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_MET2, DRV_FTM_SRAM5);
    ArbTable_Write;

    /* Fib Share SRAM 6 */
    ArbTable_Init(6);
    SRAM_Process2(6, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM6);
    SRAM_Process2(6, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM6);
    SRAM_Process(6, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM6);
    SRAM_Process(6, DRV_FTM_SRAM_TBL_ANT_FLOW, DRV_FTM_SRAM6);
    SRAM_Process(6, DRV_FTM_SRAM_TBL_ANT_FLOW2, DRV_FTM_SRAM6);
    SRAM_Process(6, DRV_FTM_SRAM_TBL_MET2, DRV_FTM_SRAM6);
    SRAM_Process2(6, DRV_FTM_SRAM_TBL_FIB1_HASH_KEY, DRV_FTM_SRAM6);/*RTL Modify*/
    ArbTable_Write;

    /* Fib Share SRAM 7 */
    ArbTable_Init(7);
    SRAM_Process2(7, DRV_FTM_SRAM_TBL_LPM_LKP_KEY0, DRV_FTM_SRAM7);
    SRAM_Process2(7, DRV_FTM_SRAM_TBL_LPM_LKP_KEY1, DRV_FTM_SRAM7);
    SRAM_Process(7, DRV_FTM_SRAM_TBL_FLOW_HASH_KEY, DRV_FTM_SRAM7);
    SRAM_Process(7, DRV_FTM_SRAM_TBL_ANT_FLOW, DRV_FTM_SRAM7);
    SRAM_Process(7, DRV_FTM_SRAM_TBL_ANT_FLOW2, DRV_FTM_SRAM7);
    SRAM_Process(7, DRV_FTM_SRAM_TBL_MET2, DRV_FTM_SRAM7);
    SRAM_Process2(7, DRV_FTM_SRAM_TBL_FIB1_HASH_KEY, DRV_FTM_SRAM7);/*RTL Modify*/
    ArbTable_Write;

    /* Fib Share SRAM 8 */
    ArbTable_Init(8);
    SRAM_Process(8, DRV_FTM_SRAM_TBL_FIB0_HASH_KEY, DRV_FTM_SRAM8);
    SRAM_Process(8, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM8);
    ArbTable_Write;

    /* Fib Share SRAM 9 */
    ArbTable_Init(9);
    SRAM_Process(9, DRV_FTM_SRAM_TBL_FIB0_HASH_KEY, DRV_FTM_SRAM9);
    SRAM_Process(9, DRV_FTM_SRAM_TBL_XKEY, DRV_FTM_SRAM9);
    ArbTable_Write;


#undef  ArbTable
#undef  ArbTblFld
#undef  ArbTblFldCouple
#undef  ArbTblFldCoupleMode
#define ArbTable(i) DynamicMiscRam##i##Ctl_t
#define ArbTblFld(i, fld) DynamicMiscRam##i##Ctl_shareMiscRam##i##fld##_f
#define ArbTblFldCouple(i, fld) DynamicMiscRam##i##Ctl_shareMiscRam##i##Local##fld##_f
#define ArbTblFldCoupleMode(i) DynamicMiscRam##i##Ctl_shareMiscRam##i##CoupleMode_f

    /* Misc Share SRAM 0 */
    ArbTable_Init(0);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_MPLS_HASH_KEY, DRV_FTM_SRAM10);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_USERID_HASH_KEY, DRV_FTM_SRAM10);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_FIB1_HASH_KEY, DRV_FTM_SRAM10);
    ArbTable_Write;

    /* Misc Share SRAM 1 */
    ArbTable_Init(1);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_MPLS_HASH_KEY, DRV_FTM_SRAM11);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_USERID_HASH_KEY, DRV_FTM_SRAM11);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_FIB1_HASH_KEY, DRV_FTM_SRAM11);
    ArbTable_Write;

#undef  ArbTable
#undef  ArbTblFld
#undef  ArbTblFldCouple
#undef  ArbTblFldCoupleMode
#define ArbTable(i) DynamicAdShareRam##i##Ctl_t
#define ArbTblFld(i, fld) DynamicAdShareRam##i##Ctl_shareAdRam##i##fld##_f
#define ArbTblFldCouple(i, fld) DynamicAdShareRam##i##Ctl_shareAdRam##i##Local##fld##_f
#define ArbTblFldCoupleMode(i) DynamicAdShareRam##i##Ctl_shareAdRam##i##CoupleMode_f

    /* Ad Share SRAM 0 */
    ArbTable_Init(0);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_MPLS_HASH_AD, DRV_FTM_SRAM21);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_DSMAC_AD, DRV_FTM_SRAM21);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_DSIP_AD, DRV_FTM_SRAM21);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_FLOW_AD, DRV_FTM_SRAM21);
    SRAM_Process(0, DRV_FTM_SRAM_TBL_XKEY2, DRV_FTM_SRAM21);
    ArbTable_Write;

    /* Ad Share SRAM 1 */
    ArbTable_Init(1);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_DSIP_AD, DRV_FTM_SRAM22);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_FLOW_AD, DRV_FTM_SRAM22);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_USERID_AD, DRV_FTM_SRAM22);
    SRAM_Process(1, DRV_FTM_SRAM_TBL_XKEY2, DRV_FTM_SRAM22);
    ArbTable_Write;

    /* Ad Share SRAM 2 */
    ArbTable_Init(2);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_MPLS_HASH_AD, DRV_FTM_SRAM23);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_DSMAC_AD, DRV_FTM_SRAM23);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_FLOW_AD, DRV_FTM_SRAM23);
    SRAM_Process(2, DRV_FTM_SRAM_TBL_USERID_AD, DRV_FTM_SRAM23);
    ArbTable_Write;


    /* Ad Share SRAM 3 */
    ArbTable_Init(3);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_DSMAC_AD, DRV_FTM_SRAM24);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_DSIP_AD, DRV_FTM_SRAM24);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_FLOW_AD, DRV_FTM_SRAM24);
    SRAM_Process(3, DRV_FTM_SRAM_TBL_USERID_AD, DRV_FTM_SRAM24);
    ArbTable_Write;

    /* Ad Share SRAM 4 */
    ArbTable_Init(4);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_DSIP_AD, DRV_FTM_SRAM25);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_USERID_AD, DRV_FTM_SRAM25);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_USERID_AD1, DRV_FTM_SRAM25);
    SRAM_Process(4, DRV_FTM_SRAM_TBL_XKEY2, DRV_FTM_SRAM25);
    ArbTable_Write;

    /* Ad Share SRAM 5 */
    ArbTable_Init(5);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_DSMAC_AD, DRV_FTM_SRAM26);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_USERID_AD, DRV_FTM_SRAM26);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_USERID_AD1, DRV_FTM_SRAM26);
    SRAM_Process(5, DRV_FTM_SRAM_TBL_XKEY2, DRV_FTM_SRAM26);
    ArbTable_Write;


    return DRV_E_NONE;
}

#define DRV_FTM_FIB_KEY_RAM_NUM 10
#define DRV_FTM_MISC_KEY_RAM_NUM 11
#define DRV_FTM_AD_RAM_NUM 6
#define DRV_FTM_EDIT_RAM_NUM 8
#define DRV_FTM_TOTAL_RAM_NUM (DRV_FTM_FIB_KEY_RAM_NUM+DRV_FTM_MISC_KEY_RAM_NUM+DRV_FTM_AD_RAM_NUM+DRV_FTM_EDIT_RAM_NUM)

#define DRV_FTM_FIB_KEY_RAM_START 0
#define DRV_FTM_MISC_KEY_RAM_START (DRV_FTM_FIB_KEY_RAM_NUM)
#define DRV_FTM_AD_RAM_START  (DRV_FTM_FIB_KEY_RAM_NUM + DRV_FTM_MISC_KEY_RAM_NUM)
#define DRV_FTM_EDIT_RAM_START (DRV_FTM_FIB_KEY_RAM_NUM + DRV_FTM_MISC_KEY_RAM_NUM + DRV_FTM_AD_RAM_NUM)

static inline uint8 _drv_at_ftm_lookup_same_group_memid(uint8 lchip, uint8 ram_id, uint32* out_ram_id)
{
    uint16 tbl_type;
    uint8 counter = 0;
    uint16 tmp_ram_id=0;
    for(tbl_type=0; tbl_type < DRV_FTM_SRAM_TBL_MAX; tbl_type++)
    {
        if(!DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(tbl_type), ram_id))
        {
            continue;
        }
        for(tmp_ram_id=0; tmp_ram_id<DRV_FTM_TOTAL_RAM_NUM; tmp_ram_id++)
        {
            if(DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(tbl_type), tmp_ram_id))
            {
                out_ram_id[counter++] = tmp_ram_id;
            }
        }
        break;
    }
    return counter;
}
uint32 _drv_at_dynamic_grp_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 ds[MAX_ENTRY_WORD] = {0};
    uint32 out_ram_id[12];
    uint32 group_en = 1;
#undef ArbTable
#undef ArbTblGroupMemId
#undef ArbTblGroupEn
#undef SetArbGroupMemID
#undef SetArbGroup
#define ArbTable(i) DynamicKeyShareRam##i##Ctl_t
#define ArbTblGroupMemId(i, memid) DynamicKeyShareRam##i##Ctl_shareKeyRam##i##GroupMemId##memid##_f
#define ArbTblGroupEn(i) DynamicKeyShareRam##i##Ctl_shareKeyRam##i##GroupModeEn##_f
#define SetArbGroupMemID(i,j,cnt,out_ram_id)\
do{uint32 ram_id = (j < cnt) ? out_ram_id[j]:0xF;\
        DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupMemId(i,j), &ram_id, ds);\
    }while(0)

#define SetArbGroup(i) \
do{\
    uint8 ram_cnt = _drv_at_ftm_lookup_same_group_memid(lchip, i, out_ram_id);\
    cmd = DRV_IOR(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
    SetArbGroupMemID(i, 0, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 1, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 2, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 3, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 4, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 5, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 6, ram_cnt, out_ram_id);\
    DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupEn(i), &group_en, ds);\
    cmd = DRV_IOW(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
}while(0)

    SetArbGroup(0);
    SetArbGroup(1);
    SetArbGroup(2);
    SetArbGroup(3);
    SetArbGroup(4);
    SetArbGroup(5);
    SetArbGroup(6);
    SetArbGroup(7);
    SetArbGroup(8);
    SetArbGroup(9);

#undef ArbTable
#undef ArbTblGroupMemId
#undef ArbTblGroupEn
#undef SetArbGroupMemID
#undef SetArbGroup
#define ArbTable(i) DynamicMiscRam##i##Ctl_t
#define ArbTblGroupMemId(i, memid) DynamicMiscRam##i##Ctl_shareMiscRam##i##GroupMemId##memid##_f
#define ArbTblGroupEn(i) DynamicMiscRam##i##Ctl_shareMiscRam##i##GroupModeEn##_f
#define SetArbGroupMemID(i,j,cnt,out_ram_id)\
do{uint32 ram_id = (j < cnt) ? (out_ram_id[j]-DRV_FTM_MISC_KEY_RAM_START):0xF;\
        DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupMemId(i,j), &ram_id, ds);\
    }while(0)

#define SetArbGroup(i) \
do{\
    uint8 ram_cnt = _drv_at_ftm_lookup_same_group_memid(lchip, i+DRV_FTM_MISC_KEY_RAM_START, out_ram_id);\
    cmd = DRV_IOR(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
    SetArbGroupMemID(i, 0, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 1, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 2, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 3, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 4, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 5, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 6, ram_cnt, out_ram_id);\
    DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupEn(i), &group_en, ds);\
    cmd = DRV_IOW(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
}while(0)

    SetArbGroup(0);
    SetArbGroup(1);
    SetArbGroup(2);
    SetArbGroup(3);
    SetArbGroup(4);
    SetArbGroup(5);
    SetArbGroup(6);
    SetArbGroup(7);
    SetArbGroup(8);
    SetArbGroup(9);
    SetArbGroup(10);

#undef ArbTable
#undef ArbTblGroupMemId
#undef ArbTblGroupEn
#undef SetArbGroupMemID
#undef SetArbGroup
#define ArbTable(i) DynamicAdShareRam##i##Ctl_t
#define ArbTblGroupMemId(i, memid) DynamicAdShareRam##i##Ctl_shareAdRam##i##GroupMemId##memid##_f
#define ArbTblGroupEn(i) DynamicAdShareRam##i##Ctl_shareAdRam##i##GroupModeEn##_f
#define SetArbGroupMemID(i,j,cnt,out_ram_id)\
do{uint32 ram_id = (j < cnt) ? (out_ram_id[j]-DRV_FTM_AD_RAM_START):0xF;\
        DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupMemId(i,j), &ram_id, ds);\
    }while(0)

#define SetArbGroup(i) \
do{\
    uint8 ram_cnt = _drv_at_ftm_lookup_same_group_memid(lchip, i+DRV_FTM_AD_RAM_START, out_ram_id);\
    cmd = DRV_IOR(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
    SetArbGroupMemID(i, 0, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 1, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 2, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 3, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 4, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 5, ram_cnt, out_ram_id);\
    DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupEn(i), &group_en, ds);\
    cmd = DRV_IOW(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
}while(0)

    SetArbGroup(0);
    SetArbGroup(1);
    SetArbGroup(2);
    SetArbGroup(3);
    SetArbGroup(4);
    SetArbGroup(5);

#undef ArbTable
#undef ArbTblGroupMemId
#undef ArbTblGroupEn
#undef SetArbGroupMemID
#undef SetArbGroup
#define ArbTable(i) DynamicEditShareRam##i##Ctl_t
#define ArbTblGroupMemId(i, memid) DynamicEditShareRam##i##Ctl_shareEditRam##i##GroupMemId##memid##_f
#define ArbTblGroupEn(i) DynamicEditShareRam##i##Ctl_shareEditRam##i##GroupModeEn##_f
#define SetArbGroupMemID(i,j,cnt,out_ram_id)\
do{uint32 ram_id = (j < cnt) ? (out_ram_id[j]-DRV_FTM_EDIT_RAM_START):0xF;\
        DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupMemId(i,j), &ram_id, ds);\
    }while(0)

#define SetArbGroup(i) \
do{\
    uint8 ram_cnt = _drv_at_ftm_lookup_same_group_memid(lchip, i+DRV_FTM_EDIT_RAM_START, out_ram_id);\
    cmd = DRV_IOR(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
    SetArbGroupMemID(i, 0, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 1, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 2, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 3, ram_cnt, out_ram_id);\
    SetArbGroupMemID(i, 4, ram_cnt, out_ram_id);\
    DRV_IOW_FIELD(lchip, ArbTable(i), ArbTblGroupEn(i), &group_en, ds);\
    cmd = DRV_IOW(ArbTable(i), DRV_ENTRY_FLAG);\
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));\
}while(0)

    SetArbGroup(0);
    SetArbGroup(1);
    SetArbGroup(2);
    SetArbGroup(3);
    SetArbGroup(4);
    SetArbGroup(5);
    SetArbGroup(6);
    SetArbGroup(7);
    //SetArbGroup(8);
    return DRV_E_NONE;
}

static int32
_drv_at_flow_lkup_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 ds[MAX_ENTRY_WORD] = {0};
    uint32 en = 0;
    uint32 mem_alloced = 0;
    uint32 mac_alloced = 0;
    uint32 mem_size = 0;
    uint8  i = 0;
    uint32 bitmap = 0;
    uint32 sram_array[16] = {0};
    uint8  sram_type = 0;
    uint32 couple_mode = 0;
    uint8  multi = 1;
    uint32 poly = 0;
    uint8 gchip_id = 0;
    uint32 couple_number = 0;
    uint32 non_couple_number = 0;
    uint32 unused_number = 0;
    FibAccelerationCtl_m fib_acc_ctl;

    /****************************************************
    Flow lkup ctl
    *****************************************************/
    sal_memset(ds, 0, sizeof(ds));

    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_FLOW_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    /* mem profile comment always couple, but chip support couple or no */
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    i  = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_0_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_0_hashType_f,   ds, poly);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_1_hashEn_f,             ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_1_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_1_indexBase_f,      ds, mem_alloced);
    mem_alloced  += en? DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]) : 0;

    i = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_2_hashEn_f,             ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_2_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_2_indexBase_f,      ds, mem_alloced);
    mem_alloced  += en? DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]) : 0;

    i  = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_3_hashEn_f,             ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_3_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_3_indexBase_f,      ds, mem_alloced);
    mem_alloced  += en? DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]) : 0;

    i  = 4;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_4_hashEn_f,             ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_4_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_4_indexBase_f,      ds, mem_alloced);

    i  = 5;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_5_hashEn_f,             ds, en);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_5_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, FlowHashLookupCtl_t,   FlowHashLookupCtl_flowHashLevel_5_indexBase_f,      ds, mem_alloced);

    cmd = DRV_IOW(FlowHashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*xlookup0 lkup ctl*/
       sal_memset(ds, 0, sizeof(ds));
       mem_alloced = 0;
       sram_type = DRV_FTM_SRAM_TBL_XKEY;
       sal_memset(sram_array, 0, sizeof(sram_array));
       _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
       /* mem profile comment always couple, but chip support couple or no */
       DRV_IF_ERROR_RETURN(drv_usw_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));
       multi = (couple_mode?2:1);

       i = 0;
       en = DRV_IS_BIT_SET(bitmap, i);
       _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_0_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_0_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_0_indexBase_f,      ds, mem_alloced);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM0))*multi) : 0;

    i = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_1_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_1_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_1_indexBase_f,      ds, mem_alloced);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM1))*multi) : 0;

    i = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_2_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_2_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_2_indexBase_f,      ds, mem_alloced);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2))*multi) : 0;

    i = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_3_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_3_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_3_indexBase_f,      ds, mem_alloced);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM3))*multi) : 0;

    i = 4;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_4_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_4_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_4_indexBase_f,      ds, mem_alloced);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM8))*multi) : 0;

    i = 5;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_5_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_5_hashType_f,     ds, poly);
    DRV_SET_FIELD_V(lchip, XLookup0Ctl_t,   XLookup0Ctl_lookup0HashLevel_5_indexBase_f,      ds, mem_alloced);

    cmd = DRV_IOW(XLookup0Ctl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*xlookup1 lkup ctl*/
    sal_memset(ds, 0, sizeof(ds));

       /*xlookup1 lkup ctl*/
       mem_alloced = 0;
       sram_type = DRV_FTM_SRAM_TBL_XKEY2;
       sal_memset(sram_array, 0, sizeof(sram_array));
       _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
       /* mem profile comment always couple, but chip support couple or no */
       DRV_IF_ERROR_RETURN(drv_usw_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));
       multi = (couple_mode?2:1);

       i = 0;
       en = DRV_IS_BIT_SET(bitmap, i);
       _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_0_hashEn_f,     ds, en);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_0_hashType_f,     ds, poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_0_indexBase_f,      ds, mem_alloced);
       mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM21))*multi) : 0;

       i = 1;
       en = DRV_IS_BIT_SET(bitmap, i);
       _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_1_hashEn_f,     ds, en);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_1_hashType_f,     ds, poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_1_indexBase_f,      ds, mem_alloced);
       mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM22))*multi) : 0;

       i = 2;
       en = DRV_IS_BIT_SET(bitmap, i);
       _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_2_hashEn_f,     ds, en);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_2_hashType_f,     ds, poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_2_indexBase_f,      ds, mem_alloced);
       mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM25))*multi) : 0;

       i = 3;
       en = DRV_IS_BIT_SET(bitmap, i);
       _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_3_hashEn_f,     ds, en);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_3_hashType_f,     ds, poly);
       DRV_SET_FIELD_V(lchip, XLookup1Ctl_t,   XLookup1Ctl_lookup1HashLevel_3_indexBase_f,      ds, mem_alloced);

       cmd = DRV_IOW(XLookup1Ctl_t, DRV_ENTRY_FLAG);
       DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    /*userid lkup ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_USERID_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type,   &bitmap,   sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    multi = (couple_mode?2:1);
    i  = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_0_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_0_hashType_f,   ds, poly);
    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i])*multi:0;

    i  = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_1_hashEn_f,      ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_1_hashType_f,    ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_1_indexBase_f,   ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_2_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_2_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_2_indexBase_f,  ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_3_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_3_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_3_indexBase_f,  ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 4;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_4_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_4_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_4_indexBase_f,  ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 5;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_5_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_5_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl0Level_5_indexBase_f,  ds, mem_alloced);

    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_USERID1_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type,   &bitmap,   sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    i  = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_0_hashEn_f,     ds, en);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_0_hashType_f,   ds, poly);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_1_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_1_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_1_indexBase_f,  ds, mem_alloced);
    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_2_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_2_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_2_indexBase_f,  ds, mem_alloced);
    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_3_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_3_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_3_indexBase_f,  ds, mem_alloced);

    i  = 4;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_4_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_4_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_4_indexBase_f,  ds, mem_alloced);
/*
user id only support 0-4 ram
    i  = 5;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_5_hashEn_f,     ds, en);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_5_hashType_f,   ds, poly);
    DRV_SET_FIELD_V(lchip, UserIdHashLookupCtl_t,   UserIdHashLookupCtl_scl1Level_5_indexBase_f,  ds, mem_alloced);
*/
    cmd = DRV_IOW(UserIdHashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*EgrScl0 lkup ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type,   &bitmap,   sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));
    i = 0;

    en = DRV_IS_BIT_SET(bitmap, i) && (g_at_ftm_master[lchip]->nsh_mode != DRV_FTM_NSH_MODE_ESCL0);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_0_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_0_hashType_f, ds, poly);
    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_1_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_1_hashType_f, ds, poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_1_indexBase_f, ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_2_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_2_hashType_f, ds, poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_2_indexBase_f, ds, mem_alloced);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_3_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_3_hashType_f, ds, poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl0Level_3_indexBase_f, ds, mem_alloced);

    /*EgrScl1 lkup ctl*/
    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type,   &bitmap,   sram_array);

    i = 0;
    en = DRV_IS_BIT_SET(bitmap, i) && (g_at_ftm_master[lchip]->nsh_mode != DRV_FTM_NSH_MODE_ESCL1);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl1Level_0_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl1Level_0_hashType_f, ds, poly);
    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl1Level_1_hashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl1Level_1_hashType_f, ds, poly);
    DRV_SET_FIELD_V(lchip, EgressSclHashLookupCtl_t, EgressSclHashLookupCtl_egressScl1Level_1_indexBase_f, ds, mem_alloced);
    cmd = DRV_IOW(EgressSclHashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*Host0lkup ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;
    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    drv_get_gchip_id(lchip, &gchip_id);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_chipId_f, &fib_acc_ctl, gchip_id);

    sram_type = DRV_FTM_SRAM_TBL_MAC_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    multi = (couple_mode?2:1);

    i  = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM0, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_0_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_0_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_0_couple_f,         ds, couple_mode);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM0))*multi) : 0;
    couple_number = 0;
    non_couple_number = 16;
    unused_number = 32;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex0_f,    &fib_acc_ctl, mac_alloced + 32); /*level 0 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level0MacHashEn_f, &fib_acc_ctl, en);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level0SizeMode_f,  &fib_acc_ctl, couple_mode);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_coupleNumber_f,  &fib_acc_ctl, couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_nonCoupleNumber_f,  &fib_acc_ctl, non_couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_unusedNumber_f,  &fib_acc_ctl, unused_number);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM0))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM0))*2;

    i  = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM1, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_1_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_1_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_1_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_1_indexBase_f,      ds, mem_alloced);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM1))*multi) : 0;
    couple_number = 0;
    non_couple_number = 16;
    unused_number = 32;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex1_f,    &fib_acc_ctl, mac_alloced + 32); /*level 1 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level1MacHashEn_f, &fib_acc_ctl, en);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level1SizeMode_f,  &fib_acc_ctl, couple_mode);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_1_coupleNumber_f,  &fib_acc_ctl, couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_1_nonCoupleNumber_f,  &fib_acc_ctl, non_couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_1_unusedNumber_f,  &fib_acc_ctl, unused_number);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM1))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM1))*2;

    i  = 2;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM2, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_2_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_2_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_2_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_2_indexBase_f,      ds, mem_alloced);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2))*multi) : 0;
    couple_number = 32;
    non_couple_number = 64;
    unused_number = 96;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex2_f,    &fib_acc_ctl, mac_alloced + 32); /*level 2 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level2MacHashEn_f, &fib_acc_ctl, en);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level2SizeMode_f,  &fib_acc_ctl, couple_mode);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_2_coupleNumber_f,  &fib_acc_ctl, couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_2_nonCoupleNumber_f,  &fib_acc_ctl, non_couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_2_unusedNumber_f,  &fib_acc_ctl, unused_number);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM2))*2;

    i  = 3;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM3, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_3_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_3_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_3_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_3_indexBase_f,      ds, mem_alloced);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM3))*multi) : 0;
    couple_number = 32;
    non_couple_number = 64;
    unused_number = 96;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex3_f,    &fib_acc_ctl, mac_alloced + 32); /*level 3 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level3MacHashEn_f, &fib_acc_ctl, en);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level3SizeMode_f,  &fib_acc_ctl, couple_mode);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_3_coupleNumber_f,  &fib_acc_ctl, couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_3_nonCoupleNumber_f,  &fib_acc_ctl, non_couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_3_unusedNumber_f,  &fib_acc_ctl, unused_number);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM3))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM3))*2;

    i  = 4;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM4, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_4_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_4_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_4_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_4_indexBase_f,      ds, mem_alloced);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4))*multi) : 0;
    couple_number = 64;
    non_couple_number = 128;
    unused_number = 192;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex4_f,    &fib_acc_ctl, mac_alloced + 32); /*level 4 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level4MacHashEn_f, &fib_acc_ctl, en);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level4SizeMode_f,  &fib_acc_ctl, couple_mode);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_4_coupleNumber_f, &fib_acc_ctl, couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_4_nonCoupleNumber_f, &fib_acc_ctl, non_couple_number);
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_4_unusedNumber_f, &fib_acc_ctl, unused_number);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM4))*2;

    i  = 5;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM5, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_5_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_5_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_5_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L2Level_5_indexBase_f,      ds, mem_alloced);
    mac_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5))*multi) : 0;
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_demarcationIndex5_f,    &fib_acc_ctl, mac_alloced + 32); /*level 5 max*/
    DRV_SET_FIELD_V(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level5MacHashEn_f, &fib_acc_ctl, en);
    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM5))*2;


    /* SDK MODIFY */
    SetFibAccelerationCtl(V, macNum_f, &fib_acc_ctl, DRV_FTM_TBL_MAX_ENTRY_NUM((DRV_IS_DUET2(lchip)?DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:DRV_FTM_SRAM_TBL_MAC_HASH_KEY))+32);

    sram_type = DRV_FTM_SRAM_TBL_FIB0_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    multi = (couple_mode?2:1);
    i  = 0;
    mem_alloced = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM8, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_0_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_0_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_0_couple_f,         ds, couple_mode);

    mem_alloced += en ? ((DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM8))*multi) : 0;
    mem_size += (DRV_FTM_MEM_MAX_ENTRY_NUM(DRV_FTM_SRAM8))*2;

    i  = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    _sys_usw_ftm_get_hash_type(lchip, sram_type, DRV_FTM_SRAM9, couple_mode, &poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_1_hashEn_f,         ds, en);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_1_hashType_f,       ds, poly);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_1_couple_f,         ds, couple_mode);
    DRV_SET_FIELD_V(lchip, FibHost0HashLookupCtl_t, FibHost0HashLookupCtl_fibHost0L3Level_1_indexBase_f,      ds, mem_alloced);
    cmd = DRV_IOW(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOW(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    /*Host1lkup ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;
    sram_type = DRV_FTM_SRAM_TBL_FIB1_HASH_KEY;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type,   &bitmap,   sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

     i  = 0;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_0_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_0_couple_f, ds, couple_mode);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_0_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_0_indexBase_f, ds, mem_alloced);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 1;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_1_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_1_couple_f, ds, couple_mode);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_1_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_1_indexBase_f, ds, mem_alloced);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 2;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_2_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_2_couple_f, ds, couple_mode);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_2_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_2_indexBase_f, ds, mem_alloced);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 3;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_3_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_3_couple_f, ds, couple_mode);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_3_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_3_indexBase_f, ds, mem_alloced);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 4;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_4_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_4_couple_f, ds, 0);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_4_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_4_indexBase_f, ds, mem_alloced);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 5;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_5_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_5_couple_f, ds, 0);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_5_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1Level_5_indexBase_f, ds, mem_alloced);

    i  = 6;
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_0_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_0_couple_f, ds, 0);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_0_hashType_f, ds, poly);
     mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

     i  = 7;
     _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
     en = DRV_IS_BIT_SET(bitmap, i);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_1_hashEn_f, ds, en);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_1_couple_f, ds, 0);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_1_hashType_f, ds, poly);
     DRV_SET_FIELD_V(lchip, FibHost1HashLookupCtl_t, FibHost1HashLookupCtl_fibHost1ExtLevel_1_indexBase_f, ds, mem_alloced);
     cmd = DRV_IOW(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
     DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*IPFix hash ctl*/
    sal_memset(ds, 0, sizeof(ds));
    en = 1;
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl0_t, IpfixHashLookupCtl0_ipfixLevel0HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl0_t, IpfixHashLookupCtl0_ipfixLevel1HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl0_t, IpfixHashLookupCtl0_ipfixLevel2HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl0_t, IpfixHashLookupCtl0_ipfixLevel3HashEn_f, ds, en);
    cmd = DRV_IOW(IpfixHashLookupCtl0_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*IPFix Egress hash ctl*/
    sal_memset(ds, 0, sizeof(ds));
    en = 1;
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl1_t, IpfixHashLookupCtl1_ipfixLevel0HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl1_t, IpfixHashLookupCtl1_ipfixLevel1HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl1_t, IpfixHashLookupCtl1_ipfixLevel2HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, IpfixHashLookupCtl1_t, IpfixHashLookupCtl1_ipfixLevel3HashEn_f, ds, en);
    cmd = DRV_IOW(IpfixHashLookupCtl1_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*Mpls hash ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;

    sram_type = DRV_FTM_SRAM_TBL_MPLS_HASH_KEY;
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    i  = 0;
    en = DRV_IS_BIT_SET(bitmap, i);
    DRV_SET_FIELD_V(lchip, MplsHashLookupCtl_t, MplsHashLookupCtl_mplsLevel0HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, MplsHashLookupCtl_t, MplsHashLookupCtl_mplsHashLookupLevel0CoupleEn_f, ds, couple_mode);

    mem_alloced += en ? DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]) : 0;

    i  = 1;
    en = DRV_IS_BIT_SET(bitmap, i);
    DRV_SET_FIELD_V(lchip, MplsHashLookupCtl_t, MplsHashLookupCtl_mplsLevel1HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, MplsHashLookupCtl_t, MplsHashLookupCtl_mplsHashLookupLevel1CoupleEn_f, ds, couple_mode);
    DRV_SET_FIELD_V(lchip, MplsHashLookupCtl_t, MplsHashLookupCtl_mplsLevel1IndexBase_f, ds, mem_alloced);

    cmd = DRV_IOW(MplsHashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /* Oam Ctl*/
    sal_memset(ds, 0, sizeof(ds));
    mem_alloced = 0;

    sram_type = DRV_FTM_SRAM_TBL_OAM_HASH_KEY;
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    DRV_IF_ERROR_RETURN(_drv_at_get_dynamic_ram_couple_mode(lchip, sram_type, &couple_mode));

    i  = 0;
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    en = DRV_IS_BIT_SET(bitmap, i);
    DRV_SET_FIELD_V(lchip, OamHashLookupCtl_t, OamHashLookupCtl_oamLevel0HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, OamHashLookupCtl_t, OamHashLookupCtl_oamLevel0HashType_f, ds, poly);

    mem_alloced  += en?DRV_FTM_TBL_MEM_ENTRY_NUM(sram_type, sram_array[i]):0;

    i  = 1;
    _sys_usw_ftm_get_hash_type(lchip, sram_type, sram_array[i], couple_mode, &poly);
    en = DRV_IS_BIT_SET(bitmap, i);
    DRV_SET_FIELD_V(lchip, OamHashLookupCtl_t, OamHashLookupCtl_oamLevel1HashEn_f, ds, en);
    DRV_SET_FIELD_V(lchip, OamHashLookupCtl_t, OamHashLookupCtl_oamLevel1HashType_f, ds, poly);
    DRV_SET_FIELD_V(lchip, OamHashLookupCtl_t, OamHashLookupCtl_oamLevel1IndexBase_f, ds, mem_alloced);

    cmd = DRV_IOW(OamHashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*lpm ctl*/
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(FibEngineLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (g_at_ftm_master[lchip]->napt_enable)
    {
        DRV_SET_FIELD_V(lchip, FibEngineLookupCtl_t, FibEngineLookupCtl_ipv4NatSaPortLookupEn_f, ds, 1);
        DRV_SET_FIELD_V(lchip, FibEngineLookupCtl_t, FibEngineLookupCtl_ipv4NatDaPortLookupEn_f, ds, 1);
        DRV_SET_FIELD_V(lchip, FibEngineLookupCtl_t, FibEngineLookupCtl_ipv6NatSaPortLookupEn_f, ds, 1);
        DRV_SET_FIELD_V(lchip, FibEngineLookupCtl_t, FibEngineLookupCtl_ipv6NatDaPortLookupEn_f, ds, 1);
    }

    cmd = DRV_IOW(FibEngineLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    sram_type = DRV_FTM_SRAM_TBL_LPM_LKP_KEY0;
    sal_memset(sram_array, 0, sizeof(sram_array));
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    SetNeoLpmCtl(V, memoryL0En_f, ds, bitmap & 0x3);
    bitmap = 0;
    sram_type = DRV_FTM_SRAM_TBL_LPM_LKP_KEY0;
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    SetNeoLpmCtl(V, memoryEn_f, ds, bitmap >> 2);
    cmd = DRV_IOW(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*NextHop Map Ctl*/
    cmd = DRV_IOR(NextHopPointerXlateCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    bitmap = 0;
    sram_type = DRV_FTM_SRAM_TBL_NHOFST_MAP;
    _drv_at_ftm_get_edram_bitmap(lchip, sram_type, &bitmap, sram_array);
    SetNextHopPointerXlateCtl(V, gMemCfg_0_memEn_f, ds, DRV_IS_BIT_SET(bitmap, 0));
    SetNextHopPointerXlateCtl(V, gMemCfg_1_memEn_f, ds, DRV_IS_BIT_SET(bitmap, 1));
    SetNextHopPointerXlateCtl(V, gMemCfg_2_memEn_f, ds, DRV_IS_BIT_SET(bitmap, 2));
    mem_size = 0;
    SetNextHopPointerXlateCtl(V, gMemCfg_0_memIndexBase_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_0_memMinIndex_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_0_memMaxIndex_f, ds, mem_size + 16383);
    mem_size += (DRV_IS_BIT_SET(bitmap, 0) ? 16384 : 0);
    SetNextHopPointerXlateCtl(V, gMemCfg_1_memIndexBase_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_1_memMinIndex_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_1_memMaxIndex_f, ds, mem_size + 4095);
    mem_size += (DRV_IS_BIT_SET(bitmap, 1) ? (16384 + 4096) : 0);
    SetNextHopPointerXlateCtl(V, gMemCfg_2_memIndexBase_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_2_memMinIndex_f, ds, mem_size);
    SetNextHopPointerXlateCtl(V, gMemCfg_2_memMaxIndex_f, ds, mem_size + 4095);
    cmd = DRV_IOW(NextHopPointerXlateCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    return DRV_E_NONE;
}
#define NUM_16K                         (16 * 1024)
#define NUM_32K                         (32 * 1024)
#define NUM_64K                         (64 * 1024)

static INLINE int32
_drv_at_ftm_get_cam_info_by_type(uint8 lchip, uint32 cam_type, uint32* table_id, uint32* cam_num)
{
    switch (cam_type)
    {
        case DRV_FTM_CAM_TYPE_FIB_HOST0:
            *table_id = DsFibHost0MacHashKey_t;
            *cam_num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM); /*DsFibHost0HashIpCam 8*4*/
            break;

        case DRV_FTM_CAM_TYPE_FIB_HOST1:
            *table_id = DsFibHost1Ipv4McastHashKey_t;
            *cam_num = DRV_CONST(DRV_FIB_HOST1_CAM_NUM); /*DsFibHost1HashCam 8*4*/
            break;

        case DRV_FTM_CAM_TYPE_FIB_MAC:
            *table_id = DsFibHost0MacHashKey_t;
            *cam_num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM); /*DsFibHost0HashMacCam 8*4*/
            break;

        case DRV_FTM_CAM_TYPE_FLOW:
            *table_id = DsFlowL2HashKey_t;
            *cam_num = DRV_CONST(DRV_FLOW_HASH_CAM_NUM); /*DsFlowHashCam_t*/
            break;

        case DRV_FTM_CAM_TYPE_XC:
            *table_id = DsOamBfdHashKey_t;
            *cam_num = DRV_CONST(DRV_OAM_HASH_CAM_NUM); /*DsEgressXcOamHashCam_t*/
            break;

        case DRV_FTM_CAM_TYPE_RMEP:
            *table_id = DsEthOamRmepRmepHashKey_t;
            *cam_num = DRV_CONST(DRV_RMEP_HASH_CAM_NUM); /*DsEthOamRmepHashCam_t*/
            break;

        case DRV_FTM_CAM_TYPE_MPLS_HASH:
            *table_id = DsMplsLabelHashKey_t;
            *cam_num = DRV_CONST(DRV_MPLS_HASH_CAM_NUM); /*DsMplsHashCam_t*/
            break;

        case DRV_FTM_CAM_TYPE_IGR_SCL0:
        case DRV_FTM_CAM_TYPE_IGR_SCL1:
        case DRV_FTM_CAM_TYPE_EGR_SCL:
        case DRV_FTM_CAM_TYPE_EGR_SCL1:
            *cam_num = 0;
            break;

        default:
            return DRV_E_INVALID_ACCESS_TYPE;
    }
    return DRV_E_NONE;
}

//TODO
static int32
_drv_at_ftm_get_cam_info(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info)
{
    uint16 index;
    uint32 table_id = 0;
    uint32 cam_num = 0;
    uint8  hash_type = 0;

    drv_acc_in_t  in;
    drv_acc_out_t out;

    sal_memset(&in, 0, sizeof(in));
    sal_memset(&out, 0, sizeof(out));

    in.type = DRV_ACC_TYPE_LOOKUP;
    in.op_type = DRV_ACC_OP_BY_INDEX;

    _drv_at_ftm_get_cam_info_by_type(lchip, p_ftm_info->tbl_type, &table_id, &cam_num);

    for(index=0; index < cam_num; index++)
    {
        switch(p_ftm_info->tbl_type)
        {
            case DRV_FTM_CAM_TYPE_FIB_HOST0:
            case DRV_FTM_CAM_TYPE_FIB_HOST1:
            case DRV_FTM_CAM_TYPE_FIB_MAC:
            case DRV_FTM_CAM_TYPE_RMEP:
            case DRV_FTM_CAM_TYPE_MPLS_HASH:
                in.tbl_id = table_id;
                in.index = index;
                drv_acc_get_hash_module(lchip,in.tbl_id, &in.module);
                DRV_IF_ERROR_RETURN(drv_acc_api(lchip, &in, &out));
                /* for all table, valid bit is in {0,0,1}*/
                if(out.data[0] && 0x01)
                {
                    p_ftm_info->used_size++;
                }
                break;

            case DRV_FTM_CAM_TYPE_FLOW:
                in.tbl_id = table_id;
                in.index = index;
                drv_acc_get_hash_module(lchip,in.tbl_id, &in.module);
                DRV_IF_ERROR_RETURN(drv_acc_api(lchip, &in, &out));
                hash_type = DRV_GET_FIELD_V(lchip, DsFlowL2HashKey_t, DsFlowL2HashKey_hashKeyType_f, &out.data);
                if(hash_type != 0)
                {
                    p_ftm_info->used_size++;
                }
                break;

           case DRV_FTM_CAM_TYPE_XC:
                in.tbl_id = table_id;
                in.index = index;
                drv_acc_get_hash_module(lchip,in.tbl_id, &in.module);
                DRV_IF_ERROR_RETURN(drv_acc_api(lchip, &in, &out));
                hash_type = DRV_GET_FIELD_V(lchip, DsOamBfdHashKey_t, DsOamBfdHashKey_hashType_f, &out.data);
                if(hash_type != 0)
                {
                    p_ftm_info->used_size++;
                }
                break;

            default:
                break;
        }
    }
    p_ftm_info->max_size = cam_num;
    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_tcam_info_detail(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info)
{
    uint8 tcam_key_type        = 0;
    uint32 tcam_key_id          = MaxTblId_t;
    uint32 tcam_ad_a[20]        = {0};
    uint32 old_key_size = 0;
    uint8 key_share_num         = 0;
    uint8 ad_share_num          = 0;
    uint32 key_size             = 0;
    uint8 index                 = 0;

    char* arr_tcam_tbl[] = {
        "IpeAcl0",
        "IpeAcl1",
        "IpeAcl2",
        "IpeAcl3",
        "IpeAcl4",
        "IpeAcl5",
        "IpeAcl6",
        "IpeAcl7",
        "IpeAcl8",
        "IpeAcl9",
        "IpeAcl10",
        "IpeAcl11",
        "IpeAcl12",
        "IpeAcl13",
        "IpeAcl14",
        "IpeAcl15",
        "IpeAcl16",
        "IpeAcl17",
        "IpeAcl18",
        "IpeAcl19",
        "IpeAcl20",
        "IpeAcl21",
        "IpeAcl22",
        "IpeAcl23",
        "EpeAcl0",
        "EpeAcl1",
        "EpeAcl2",
        "EpeAcl3",
        "EpeAcl4",
        "EpeAcl5",
        "EpeAcl6",
        "EpeAcl7",
        "EpeAcl8",
        "EpeAcl9",
        "EpeAcl10",
        "EpeAcl11",
        "IPESCL0",
        "IPESCL1",
        "IPESCL2",
        "IPESCL3",
        "EPESCL0",
        "EPESCL1",
        "LPM0All",
        "LPM0DaPrivate",
        "LPM0SaPrivate",
        "LPM0DaPublic",
        "LPM0SaPublic",
        "LPM1All",
        "Static",
        "IPv4UC",
        "IPv4NAT",
        "IPv6UC",
        "IPv6UCHalf"
    };

    tcam_key_type = p_ftm_info->tbl_type;

    _drv_at_ftm_get_tcam_info(lchip, tcam_key_type,
                             p_ftm_info->tbl_id,
                             tcam_ad_a,
                             &key_share_num,
                             &ad_share_num);
    if (0 == key_share_num || 0 == ad_share_num)
    {
        return DRV_E_NONE;
    }

    p_ftm_info->tbl_entry_num = key_share_num;

    /*tcam key alloc*/
    for (index = 0; index < key_share_num; index++)
    {
        tcam_key_id = p_ftm_info->tbl_id[index];

        if (tcam_key_id >= MaxTblId_t)
        {
            DRV_FTM_DBG_OUT("unexpect tbl id:%d\r\n", tcam_key_id);
            return DRV_E_INVAILD_TYPE;
        }

        if (0 == TABLE_FIELD_NUM(lchip, tcam_key_id))
        {
            continue;
        }

        p_ftm_info->max_idx[index]  = TABLE_MAX_INDEX(lchip, tcam_key_id);
        key_size            = TCAM_KEY_SIZE(lchip, tcam_key_id);
        if (tcam_key_type >= DRV_FTM_TCAM_TYPE_IGS_LPM0DA && tcam_key_type <= DRV_FTM_TCAM_TYPE_IGS_LPM1)
        {
            key_size            = (key_size / DRV_LPM_KEY_BYTES_PER_ENTRY) * 40;
        }
        else
        {
            key_size            = (key_size / DRV_BYTES_PER_ENTRY) * 80;
        }

        if (tcam_key_type != DRV_FTM_TCAM_TYPE_IGS_LPM1)
        {
            if (old_key_size != key_size)
            {
                p_ftm_info->key_size[index] = key_size;
            }
            else
            {
                p_ftm_info->key_size[index] = 0;
            }
        }
        else
        {
            p_ftm_info->key_size[index] = key_size;
        }

        old_key_size = key_size;

    }

    sal_strncpy(p_ftm_info->str, arr_tcam_tbl[tcam_key_type], (sizeof(p_ftm_info->str) - 1));

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_edram_info_detail(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info)
{
    uint8 mem_id = 0;
    uint8 mem_id_bit = 0;
    uint8 mem_num = 0;

    _drv_at_ftm_get_sram_tbl_name(p_ftm_info->tbl_type, p_ftm_info->str);

    for (mem_id = DRV_FTM_SRAM0; mem_id < DRV_FTM_EDRAM_MAX; mem_id++)
    {
        mem_id_bit = (mem_id >= DRV_FTM_MIXED0)?(mem_id - DRV_FTM_MIXED0):mem_id;

        if (DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(p_ftm_info->tbl_type), mem_id_bit) &&
            DRV_FTM_TBL_MEM_ENTRY_NUM(p_ftm_info->tbl_type, mem_id))
        {
            p_ftm_info->mem_id[mem_num] = mem_id;
            p_ftm_info->entry_num[mem_num] = DRV_FTM_TBL_MEM_ENTRY_NUM(p_ftm_info->tbl_type, mem_id);
            p_ftm_info->offset[mem_num] = DRV_FTM_TBL_MEM_START_OFFSET(p_ftm_info->tbl_type, mem_id);

            ++ mem_num;
        }
    }

    p_ftm_info->tbl_entry_num = mem_num;

    return DRV_E_NONE;
}

static uint32
_drv_at_ftm_memid_2_table(uint8 lchip, uint32 mem_id)
{
    uint32 table_id = MaxTblId_t;

    if (mem_id <= DRV_FTM_EDRAM_MAX)
    {
        for (table_id = 0; table_id < DRV_FTM_SRAM_TBL_MAX; table_id++)
        {
            if (DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(table_id), mem_id))
            {
                break;
            }
        }
    }
    else if(mem_id <= DRV_FTM_TCAM_ADM)
    {
        mem_id = ((mem_id <= DRV_FTM_TCAM_KEYM)? (mem_id - DRV_FTM_TCAM_KEY0): (mem_id - DRV_FTM_TCAM_AD0));
        for (table_id = 0; table_id < DRV_FTM_TCAM_TYPE_MAX; table_id++)
        {
            if (DRV_BMP_ISSET(DRV_FTM_KEY_MEM_BITMAP(table_id), mem_id))
            {
                break;
            }
        }
    }
    else if(mem_id <= DRV_FTM_LPM_TCAM_ADM)
    {
        mem_id = ((mem_id <= DRV_FTM_LPM_TCAM_KEYM)? (mem_id - DRV_FTM_LPM_TCAM_KEY0): (mem_id - DRV_FTM_LPM_TCAM_AD0));
        for (table_id = DRV_FTM_TCAM_TYPE_IGS_LPM_ALL; table_id < DRV_FTM_TCAM_TYPE_MAX; table_id++)
        {
            if (DRV_BMP_ISSET(DRV_FTM_KEY_MEM_BITMAP(table_id), mem_id))
            {
                break;
            }
        }
    }

    return table_id;
}

#define _____APIs_____


static int32
_drv_at_ftm_lookup_ctl_init(uint8 lchip)
{
    DRV_IF_ERROR_RETURN(_drv_at_tcam_ctl_init(lchip));
    DRV_IF_ERROR_RETURN(_drv_at_dynamic_arb_init(lchip));
    DRV_IF_ERROR_RETURN(_drv_at_dynamic_cam_init(lchip));
    DRV_IF_ERROR_RETURN(_drv_at_dynamic_grp_init(lchip));
    DRV_IF_ERROR_RETURN(_drv_at_flow_lkup_ctl_init(lchip));

    return DRV_E_NONE;
}


static int32
_drv_at_ftm_ext_table_type_init(uint8 lchip)
{
    uint32 index =0;
    uint32 tbl_id = 0;
    tbls_ext_info_t* p_tbl_ext_info = NULL;

    /*1. init parser table ext type*/
    for(index =0; index < sizeof(parser_tbl_id_list)/sizeof(parser_tbl_id_list[0]); index++)
    {
        tbl_id = parser_tbl_id_list[index];
        if (TABLE_EXT_INFO_PTR(lchip, tbl_id) == NULL)
        {
            p_tbl_ext_info = mem_malloc(MEM_FTM_MODULE, sizeof(tbls_ext_info_t));
            if (NULL == p_tbl_ext_info)
            {
                return DRV_E_NO_MEMORY;
            }

            sal_memset(p_tbl_ext_info, 0, sizeof(tbls_ext_info_t));
            p_tbl_ext_info->ext_type = 1;

            TABLE_EXT_INFO_PTR(lchip, tbl_id) = p_tbl_ext_info;
        }
        else
        {
            p_tbl_ext_info = TABLE_EXT_INFO_PTR(lchip, tbl_id);
            p_tbl_ext_info->ext_type = 1;
        }
    }

    return DRV_E_NONE;
}



static int32
_drv_at_ftm_set_tcam_spec(uint8 lchip, void* profile_info)
{
    uint32 entry_num = 0;
    uint8 tcam_key_type = 0;

    for (tcam_key_type = DRV_FTM_TCAM_TYPE_IGS_ACL0; tcam_key_type <= DRV_FTM_TCAM_TYPE_EGS_SCL1; tcam_key_type++)
    {

        entry_num =  DRV_FTM_KEY_MAX_INDEX(tcam_key_type);

        g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_80] = (entry_num / 4) / 1;
        g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_160]  = (entry_num / 4) / 2;
        g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_320]  = (entry_num / 4) / 4;
        g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_640] = (entry_num / 4) / 8;


        g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][DRV_FTM_TCAM_SIZE_80] = 0;
        g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][DRV_FTM_TCAM_SIZE_160] = (g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_80])/2;

        g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][DRV_FTM_TCAM_SIZE_320] = (g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_80]
                                                                            + g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_160]*2)/4;

        g_at_ftm_master[lchip]->tcam_offset[tcam_key_type][DRV_FTM_TCAM_SIZE_640] = (g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_80]
                                                                            +g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_160]*2
                                                                            +g_at_ftm_master[lchip]->tcam_specs[tcam_key_type][DRV_FTM_TCAM_SIZE_320]*4)/8;
    }

    return 0;
}

static uint8
_drv_at_ftm_sram_get_sdb_en(uint8 lchip, uint8 ram_id)
{
    uint8 loop = 0;
    uint8 sram_tbl[] = {
        DRV_FTM_SRAM_TBL_ANT_FLOW,
        DRV_FTM_SRAM_TBL_ANT_FLOW2,
        DRV_FTM_SRAM_TBL_OAM_MEP,
        DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY,
        DRV_FTM_SRAM_TBL_IPFIX_AD,
        DRV_FTM_SRAM_TBL_IPFIX_AD1
    };
    if(!DRV_BMP_ISSET(g_at_ftm_master[lchip]->mem_used, ram_id))
    {
        return FALSE;
    }
    if ((ram_id >= DRV_FTM_TCAM_AD0 && ram_id < (DRV_FTM_TCAM_AD0 + DRV_CONST(DRV_MAX_NOR_TCAM_NUM))) ||
        (ram_id >= DRV_FTM_LPM_TCAM_AD0 && ram_id < DRV_FTM_LPM_TCAM_ADM))
    {
        return TRUE;
    }
    do {
        if (ram_id < DRV_FTM_EDRAM_MAX && DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(sram_tbl[loop]), ram_id))
        {
            return FALSE;
        }
    }while(++loop < sizeof(sram_tbl));
    return TRUE;
}


#define DRV_FTM_ESCL_PER_MEM_ENTRY_NUM  8192
static int32
_drv_at_ftm_set_nsh_mode(uint8 lchip, drv_ftm_profile_info_t* profile_info)
{
    uint32 max_entry_num = 0;
    if (0 == profile_info->nsh_num)
    {
        g_at_ftm_master[lchip]->nsh_mode = DRV_FTM_NSH_MODE_NONE;
        return DRV_E_NONE;
    }

    if (profile_info->nsh_num > 4 && profile_info->nsh_num != 8)
    {
        return DRV_E_INVALID_PARAMETER;
    }

    if (DRV_FTM_TBL_MAX_ENTRY_NUM(DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY) > 0)
    {
        g_at_ftm_master[lchip]->nsh_mode = DRV_FTM_NSH_MODE_ESCL1_PART;
        max_entry_num = DRV_FTM_TBL_MAX_ENTRY_NUM(DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY);
    }
    else
    {
        g_at_ftm_master[lchip]->nsh_mode = DRV_FTM_NSH_MODE_ESCL0_PART;
        max_entry_num = DRV_FTM_TBL_MAX_ENTRY_NUM(DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY);
    }
    if (max_entry_num == DRV_FTM_ESCL_PER_MEM_ENTRY_NUM)
    {
        if (profile_info->nsh_num != 4)
        {
            return DRV_E_INVALID_PARAMETER;
        }
        /*when nsh init, occupy escl hash memory for nsh edit, index 0,1,4,5,8,9,...*/
    }
    else if (max_entry_num > DRV_FTM_ESCL_PER_MEM_ENTRY_NUM)
    {
        if (profile_info->nsh_num == 8)
        /*nsh use whole first sram of escl*/
        {
            g_at_ftm_master[lchip]->nsh_mode = (g_at_ftm_master[lchip]->nsh_mode == DRV_FTM_NSH_MODE_ESCL1_PART)
                                                    ? DRV_FTM_NSH_MODE_ESCL1
                                                    : DRV_FTM_NSH_MODE_ESCL0;
        }
        else
        /*when nsh init, occupy escl hash memory for nsh edit, index 0,1,2,3,...*/
        /*warning, this mode escl hash conflict rate increases*/
        {
            ;
        }
    }
    return DRV_E_NONE;
}

static int32
_drv_at_ftm_mem_alloc(uint8 lchip, void* p_profile_info)
{
    drv_ftm_profile_info_t *profile_info = (drv_ftm_profile_info_t *)p_profile_info;

    DRV_PTR_VALID_CHECK(profile_info);

    if ((profile_info->profile_type >= 1)
        && ((profile_info->profile_type != 12)))
    {
        return DRV_E_INVAILD_TYPE;
    }
#if (SDK_WORK_PLATFORM == 1)
extern uint8 g_drv_vchip_mode;
    if (lchip && g_drv_vchip_mode)
    {
        return DRV_E_NONE;
    }
#endif
    /*init global param*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_init(lchip, profile_info));
    if (lchip != drv_vchip_get_pp_base(lchip))
    {
        return DRV_E_NONE;
    }


    /*init hash poly*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_init_hash_poly(lchip));

    DRV_IF_ERROR_RETURN(_drv_at_set_dynamic_ram_couple_mode(lchip, profile_info->couple_mode));

    /*set profile*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_profile(lchip, profile_info));

    /*alloc hash table*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_alloc_sram(lchip));

    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_nsh_mode(lchip, profile_info));

    /* alloc tcam table*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_alloc_tcam(lchip));

    /* alloc static table*/
    DRV_IF_ERROR_RETURN(_drv_at_ftm_alloc_static(lchip));

    DRV_IF_ERROR_RETURN(_drv_at_ftm_ext_table_type_init(lchip));

    DRV_IF_ERROR_RETURN(_drv_at_ftm_set_tcam_spec(lchip, profile_info));


    return DRV_E_NONE;
}
static int32
_drv_at_ftm_mem_free(uint8 lchip)
{
    uint8 loop = 0;
    tbls_id_t tbl_id = 0;
    uint32 mem_id;

#if (SDK_WORK_PLATFORM == 1)
extern uint8 g_drv_vchip_mode;
    if (((g_drv_vchip_mode && !lchip)) || lchip != drv_vchip_get_pp_base(lchip))
    {
        g_at_ftm_master[lchip] = NULL;
        return DRV_E_NONE;
    }
#endif

    for(tbl_id=0; tbl_id < MaxTblId_t; tbl_id++)
    {
        if(!TABLE_EXT_INFO_PTR(lchip, tbl_id))
        {
            continue;
        }

        if(TABLE_EXT_INFO_PTR(lchip, tbl_id)->ptr_ext_content)
        {
            if((TABLE_EXT_INFO_TYPE(lchip, tbl_id) == DRV_TABLE_TYPE_TCAM) ||
                (TABLE_EXT_INFO_TYPE(lchip, tbl_id) == DRV_TABLE_TYPE_TCAM_AD) ||
                (TABLE_EXT_INFO_TYPE(lchip, tbl_id) == DRV_TABLE_TYPE_STATIC_TCAM_KEY) ||
                (TABLE_EXT_INFO_TYPE(lchip, tbl_id) == DRV_TABLE_TYPE_DYNAMIC))
            {
                if((TABLE_EXT_INFO_TYPE(lchip, tbl_id) != DRV_TABLE_TYPE_DYNAMIC) && TCAM_EXT_INFO_PTR(lchip, tbl_id)->hw_mask_base)
                {
                    mem_free(TCAM_EXT_INFO_PTR(lchip, tbl_id)->hw_mask_base);
                }
            }
            mem_free(TABLE_EXT_INFO_PTR(lchip, tbl_id)->ptr_ext_content);
        }
        mem_free(TABLE_EXT_INFO_PTR(lchip, tbl_id));
    }



    if(!g_at_ftm_master[lchip])
    {
        return DRV_E_NONE;
    }

    if (g_at_ftm_master[lchip]->p_tcam_key_info)
    {
        mem_free(g_at_ftm_master[lchip]->p_tcam_key_info);
    }
    if (g_at_ftm_master[lchip]->p_sram_tbl_info)
    {
        for (tbl_id = DRV_FTM_SRAM_TBL_MAC_HASH_KEY; tbl_id < DRV_FTM_SRAM_TBL_MAX; tbl_id++)
        {
            if (g_at_ftm_master[lchip]->p_sram_tbl_info[tbl_id].sram_part_a)
            {
                mem_free(g_at_ftm_master[lchip]->p_sram_tbl_info[tbl_id].sram_part_a);
            }
        }
        for (mem_id = 0; mem_id < DRV_FTM_SRAM_MAX; mem_id++)
        {
            if (DRV_FTM_SRAM_DB(mem_id).part)
            {
                mem_free(DRV_FTM_SRAM_DB(mem_id).part);
            }
        }
        mem_free(g_at_ftm_master[lchip]->p_sram_tbl_info);
    }
    mem_free(g_at_ftm_master[lchip]);
    for (loop = lchip + 1; loop < lchip + drv_vchip_get_pp_num(lchip); loop++)
    {
        g_at_ftm_master[loop] = NULL;
    }
#if (SDK_WORK_PLATFORM == 1)
extern uint8 g_drv_vchip_mode;
    if (g_drv_vchip_mode)
    {
        for (loop = 0; loop < drv_vchip_get_pp_num(lchip); loop++)
        {
            g_at_ftm_master[loop] = NULL;
        }
    }
#endif
    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_info_detail(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info)
{
    DRV_INIT_CHECK(lchip);
    switch (p_ftm_info->info_type)
    {
        case DRV_FTM_INFO_TYPE_CAM:
            DRV_IF_ERROR_RETURN(_drv_at_ftm_get_cam_info(lchip, p_ftm_info));
            break;
        case DRV_FTM_INFO_TYPE_TCAM:
            DRV_IF_ERROR_RETURN(_drv_at_ftm_get_tcam_info_detail(lchip, p_ftm_info));
            break;
        case DRV_FTM_INFO_TYPE_EDRAM:
            DRV_IF_ERROR_RETURN(_drv_at_ftm_get_edram_info_detail(lchip, p_ftm_info));
            break;

        case DRV_FTM_INFO_TYPE_LPM_MODEL:
            p_ftm_info->l3.lpm_model = g_at_ftm_master[lchip]->lpm_model;
            break;
        case DRV_FTM_INFO_TYPE_NAT_PBR_EN:
            p_ftm_info->l3.nat_pbr_en = g_at_ftm_master[lchip]->nat_pbr_enable;
            break;
        case DRV_FTM_INFO_TYPE_LPM_TCAM_INIT_SIZE:
            DRV_IF_ERROR_RETURN(drv_usw_ftm_get_lpm_tcam_init_size(lchip, g_at_ftm_master[lchip]->lpm_model,
                                    g_at_ftm_master[lchip]->lpm_tcam_init_bmp, p_ftm_info));
            break;
        case DRV_FTM_INFO_TYPE_SCL_MODE:
            p_ftm_info->scl_mode = g_at_ftm_master[lchip]->scl_mode;
            break;
        default:
            break;
    }
    p_ftm_info->nsh_mode = g_at_ftm_master[lchip]->nsh_mode;

    return DRV_E_NONE;
}


static int32
_drv_at_ftm_get_sram_type(uint8 lchip, uint32 mem_id, uint8* p_sram_type)
{
    uint8 sram_type = 0;
    for (sram_type = DRV_FTM_SRAM_TBL_MAC_HASH_KEY; sram_type <= DRV_FTM_SRAM_TBL_OAM_HASH_KEY; sram_type++)
    {
        if (DRV_BMP_ISSET(DRV_FTM_TBL_MEM_BITMAP(sram_type), mem_id))
        {
            break;
        }
    }

    *p_sram_type = sram_type;

    return DRV_E_NONE;
}
static int32
_drv_at_ftm_op_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type, uint8 is_set, uint32* drv_poly)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;

    switch (sram_type)
    {
        case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
            tbl_id = FlowHashLookupCtl_t;
            switch (mem_id)
            {
                case DRV_FTM_SRAM2:
                    fld_id = FlowHashLookupCtl_flowHashLevel_0_hashType_f;
                    break;

                case DRV_FTM_SRAM3:
                    fld_id = FlowHashLookupCtl_flowHashLevel_1_hashType_f;
                    break;

                case DRV_FTM_SRAM4:
                    fld_id = FlowHashLookupCtl_flowHashLevel_2_hashType_f;
                    break;

                case DRV_FTM_SRAM5:
                    fld_id = FlowHashLookupCtl_flowHashLevel_3_hashType_f;
                    break;

                case DRV_FTM_SRAM6:
                    fld_id = FlowHashLookupCtl_flowHashLevel_4_hashType_f;
                    break;

                case DRV_FTM_SRAM7:
                    fld_id = FlowHashLookupCtl_flowHashLevel_5_hashType_f;
                    break;

                default:
                    return DRV_E_INVALID_MEM;
            }

            break;
        case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
            tbl_id = UserIdHashLookupCtl_t;
            switch (mem_id)
            {
                case DRV_FTM_SRAM10:
                    fld_id = UserIdHashLookupCtl_scl0Level_0_hashType_f;
                    break;

                case DRV_FTM_SRAM11:
                    fld_id = UserIdHashLookupCtl_scl0Level_1_hashType_f;
                    break;

                case DRV_FTM_SRAM12:
                    fld_id = UserIdHashLookupCtl_scl0Level_2_hashType_f;
                    break;

                case DRV_FTM_SRAM13:
                    fld_id = UserIdHashLookupCtl_scl0Level_3_hashType_f;
                    break;

                case DRV_FTM_SRAM14:
                    fld_id = UserIdHashLookupCtl_scl0Level_4_hashType_f;
                    break;

                case DRV_FTM_SRAM15:
                    fld_id = UserIdHashLookupCtl_scl0Level_5_hashType_f;
                    break;

                default:
                    return DRV_E_INVALID_MEM;
            }
            break;

        case DRV_FTM_SRAM_TBL_USERID1_HASH_KEY:
            tbl_id = UserIdHashLookupCtl_t;
            switch(mem_id)
            {
                case DRV_FTM_SRAM14:
                    fld_id = UserIdHashLookupCtl_scl1Level_0_hashType_f;
                    break;

                case DRV_FTM_SRAM15:
                    fld_id = UserIdHashLookupCtl_scl1Level_1_hashType_f;
                    break;

                case DRV_FTM_SRAM16:
                    fld_id = UserIdHashLookupCtl_scl1Level_2_hashType_f;
                    break;

                case DRV_FTM_SRAM17:
                    fld_id = UserIdHashLookupCtl_scl1Level_3_hashType_f;
                    break;

                case DRV_FTM_SRAM18:
                    fld_id = UserIdHashLookupCtl_scl1Level_4_hashType_f;
                    break;
                default:
                    return DRV_E_INVALID_MEM;
            }
            break;

        case DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY:
            tbl_id = EgressSclHashLookupCtl_t;
            switch(mem_id)
            {
                case DRV_FTM_SRAM17:
                    fld_id = EgressSclHashLookupCtl_egressScl0Level_0_hashType_f;
                    break;
                case DRV_FTM_SRAM18:
                    fld_id = EgressSclHashLookupCtl_egressScl0Level_1_hashType_f;
                    break;
                case DRV_FTM_SRAM19:
                    fld_id = EgressSclHashLookupCtl_egressScl0Level_2_hashType_f;
                    break;
                case DRV_FTM_SRAM20:
                    fld_id = EgressSclHashLookupCtl_egressScl0Level_3_hashType_f;
                    break;
                default:
                    return DRV_E_INVALID_MEM;
            }
            break;
        case DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY:
            tbl_id = EgressSclHashLookupCtl_t;
            switch(mem_id)
            {
                case DRV_FTM_SRAM19:
                    fld_id = EgressSclHashLookupCtl_egressScl1Level_0_hashType_f;
                    break;
                case DRV_FTM_SRAM20:
                    fld_id = EgressSclHashLookupCtl_egressScl1Level_1_hashType_f;
                    break;
                default:
                    return DRV_E_INVALID_MEM;
            }
            break;
        case DRV_FTM_SRAM_TBL_MAC_HASH_KEY:
            tbl_id = FibHost0HashLookupCtl_t;
            if (DRV_FTM_SRAM0 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_0_hashType_f;
            }
            else if (DRV_FTM_SRAM1 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_1_hashType_f;
            }
            else if (DRV_FTM_SRAM2 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_2_hashType_f;
            }
            else if (DRV_FTM_SRAM3 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_3_hashType_f;
            }
            else if (DRV_FTM_SRAM4 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_4_hashType_f;
            }
            else if(DRV_FTM_SRAM5 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L2Level_5_hashType_f;
            }
            else
            {
                return DRV_E_INVALID_MEM;
            }

            break;
        case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
            tbl_id = FibHost0HashLookupCtl_t;
            if (DRV_FTM_SRAM8 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L3Level_0_hashType_f;
            }
            else if (DRV_FTM_SRAM9 == mem_id)
            {
                fld_id = FibHost0HashLookupCtl_fibHost0L3Level_1_hashType_f;
            }
            else
            {
                return DRV_E_INVALID_MEM;
            }
            break;
        case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
            tbl_id = FibHost1HashLookupCtl_t;
            if (DRV_FTM_SRAM6 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1ExtLevel_0_hashType_f;
            }
            else if (DRV_FTM_SRAM7 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1ExtLevel_1_hashType_f;
            }
            else if (DRV_FTM_SRAM10 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_0_hashType_f;
            }
            else if (DRV_FTM_SRAM11 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_1_hashType_f;
            }
            else if (DRV_FTM_SRAM15 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_2_hashType_f;
            }
            else if (DRV_FTM_SRAM16 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_3_hashType_f;
            }
            else if (DRV_FTM_SRAM17 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_4_hashType_f;
            }
            else if (DRV_FTM_SRAM18 == mem_id)
            {
                fld_id = FibHost1HashLookupCtl_fibHost1Level_5_hashType_f;
            }
            else
            {
                return DRV_E_INVALID_MEM;
            }
            break;

        case DRV_FTM_SRAM_TBL_OAM_HASH_KEY:
            tbl_id = OamHashLookupCtl_t;
            if (DRV_FTM_SRAM41 == mem_id)
            {
                fld_id = OamHashLookupCtl_oamLevel0HashType_f;
            }
            else if (DRV_FTM_SRAM42 == mem_id)
            {
                fld_id = OamHashLookupCtl_oamLevel1HashType_f;
            }
            else
            {
                return DRV_E_INVALID_MEM;
            }
            break;
        default :
            return DRV_E_INVALID_MEM;
    }

    cmd = is_set ? DRV_IOW(tbl_id, fld_id) : DRV_IOR(tbl_id, fld_id);
    DRV_FIELD_IOCTL(lchip, 0, cmd, drv_poly);

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32* drv_poly)
{
    return _drv_at_ftm_op_hash_poly( lchip,  mem_id,  sram_type, 0, drv_poly);
}

static int32
_drv_at_ftm_set_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 drv_poly)
{
    return _drv_at_ftm_op_hash_poly( lchip,  mem_id,  sram_type, 1, &drv_poly);
}

int32
drv_at_ftm_mapping_drv_hash_poly_type(uint8 lchip, uint8 sram_type, uint32 type, uint32* p_poly)
{
    drv_ftm_hash_poly_t* p_hash_poly = &g_at_ftm_master[lchip]->p_sram_tbl_info[sram_type].hash_poly;
    uint32 sram_index = 0;

    *p_poly = 0;
    for(sram_index=0;sram_index<p_hash_poly->sram_num;sram_index++)
    {
        if (p_hash_poly->sram_poly[sram_index].poly_map[0].ctc_poly == type)
        {
            *p_poly = p_hash_poly->sram_poly[sram_index].poly_map[0].drv_poly;
            break;
        }
        if (p_hash_poly->sram_poly[sram_index].poly_map[1].ctc_poly == type)
        {
            *p_poly = p_hash_poly->sram_poly[sram_index].poly_map[1].drv_poly;
            break;
        }
    }
    return DRV_E_NONE;
}

int32
drv_at_ftm_get_current_hash_poly_type(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 *poly_type)
{
    drv_ftm_hash_poly_t* p_hash_poly = &g_at_ftm_master[lchip]->p_sram_tbl_info[sram_type].hash_poly;
    uint32 sram_index = 0;
    uint32 type = 0;

    _drv_at_ftm_get_hash_poly(lchip, mem_id, sram_type, &type);
    *poly_type = 0;
    for(sram_index=0;sram_index<p_hash_poly->sram_num;sram_index++)
    {
        if (p_hash_poly->sram_poly[sram_index].poly_map[0].drv_poly == type)
        {
            *poly_type = p_hash_poly->sram_poly[sram_index].poly_map[0].ctc_poly;
            break;
        }
        if (p_hash_poly->sram_poly[sram_index].poly_map[1].drv_poly == type)
        {
            *poly_type = p_hash_poly->sram_poly[sram_index].poly_map[1].ctc_poly;
            break;
        }
    }
    return DRV_E_NONE;
}

int32
drv_at_ftm_get_hash_poly_cap(uint8 lchip, uint8 sram_type, uint32 mem_id, uint8* poly_num, uint32* poly_type)
{
    uint32 sram_id = 0;
    uint32 ref_entry_num = DRV_FTM_SRAM_DB(mem_id).entry_num;
    uint16 sram_index = 0;
    uint8  couple_mode = DRV_FTM_TBL_COUPLE_MODE(sram_type);
    uint8  connect_id = 0;

    if (!DRV_FTM_TBL_HASH_POLY(sram_type).sram_num)
    {
        return DRV_E_NONE;
    }
    (*poly_num) = 0;
    do
    {
        sram_id = DRV_FTM_TBL_INFO(sram_type).sram_id_a[sram_index];
        connect_id = DRV_FTM_SRAM_DB(sram_id).connect_id;
        if (ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num)
        {
            poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[couple_mode].ctc_poly;
        }
        else if (DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[0].drv_poly
                 != DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[1].drv_poly)
        {
            if (!couple_mode && ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num*2)
            {
                poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[1].ctc_poly;
            }
            else if (couple_mode && ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num/2)
            {
                poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[0].ctc_poly;
            }
        }
    }while(++sram_index<DRV_FTM_TBL_INFO(sram_type).sram_num);

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_hash_drv_poly_cap(uint8 lchip, uint8 sram_type, uint32 mem_id, uint8* poly_num, uint32* poly_type)
{
    uint32 sram_id = 0;
    uint32 ref_entry_num = DRV_FTM_SRAM_DB(mem_id).entry_num;
    uint16 sram_index = 0;
    uint8  couple_mode = DRV_FTM_TBL_COUPLE_MODE(sram_type);
    uint8  connect_id = 0;

    if (!DRV_FTM_TBL_HASH_POLY(sram_type).sram_num)
    {
        return DRV_E_NONE;
    }
    (*poly_num) = 0;
    do
    {
        sram_id = DRV_FTM_TBL_INFO(sram_type).sram_id_a[sram_index];
        connect_id = DRV_FTM_SRAM_DB(sram_id).connect_id;
        if (ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num)
        {
            poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[couple_mode].drv_poly;
        }
        else if (DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[0].drv_poly
                 != DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[1].drv_poly)
        {
            if (!couple_mode && ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num*2)
            {
                poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[1].drv_poly;
            }
            else if (couple_mode && ref_entry_num == DRV_FTM_SRAM_DB(sram_id).entry_num/2)
            {
                poly_type[(*poly_num)++] = DRV_FTM_TBL_HASH_POLY(sram_type).sram_poly[connect_id].poly_map[0].drv_poly;
            }
        }
    }while(++sram_index<DRV_FTM_TBL_INFO(sram_type).sram_num);

    return DRV_E_NONE;

}
static char*
_drv_at_ftm_get_hash_poly_str(uint8 lchip, uint32 sram_type, uint32 drv_poly)
{
    switch (sram_type)
    {
        case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
            {
                char *str[] = {           \
                    "x14+x6+x5+x4+x3+x+1",\
                    "x14+x7+x5+x3+x2+x+1",\
                    "x15+x7+1",           \
                    "x15+x5+x3+x2+1",     \
                    "x15+x5+x4+x2+1",     \
                    "x15+x6+x4+x3+x2+x+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
            {
                char *str[] = {           \
                    "x12+x6+x4+x+1",      \
                    "x12+x7+x4+x3+1",     \
                    "x12+x6+x5+x3+1",     \
                    "x12+x7+x6+x4+1",     \
                    "x11+x6+x2+x+1",      \
                    "x11+x6+x5+x+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_USERID1_HASH_KEY:
            {
                char *str[] = {           \
                    "x11+x6+x2+x+1",      \
                    "x11+x6+x5+x+1",      \
                    "x11+x7+x6+x4+1",     \
                    "x11+x7+x6+x5+1",     \
                    "x11+x8+x4+x+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY:
            {
                char *str[] = {           \
                    "x11+x7+x6+x5+1",     \
                    "x11+x8+x4+x+1",      \
                    "x11+x5+x3+x+1",      \
                    "x11+x5+x3+x2+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY:
            {
                char *str[] = {
                    "1",                  \
                    "2",                  \
                    "x11+x5+x3+x+1",      \
                    "x11+x5+x3+x2+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_MAC_HASH_KEY:
            {
                char *str[] = {           \
                    "x12+x6+x4+x+1",      \
                    "x12+x7+x4+x3+1",     \
                    "x13+x6+x4+x+1",      \
                    "x13+x7+x6+x+1",      \
                    "x13+x7+x6+x3+1",     \
                    "x13+x7+x6+x5+1",     \
                    "x14+x6+x5+x4+x3+x+1",\
                    "x14+x7+x5+x3+x2+x+1",\
                    "x14+x7+x5+x4+x3+x+1",\
                    "x14+x6+x4+x3+x2+x+1",\
                    "x15+x7+1",           \
                    "x15+x5+x3+x2+1",     \
                    "x12+x6+x5+x3+1",     \
                    "x12+x7+x6+x4+1",     \
                    "x13+x7+x6+x5+x4+x+1",\
                    "x13+x8+x3+x2+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
            {
                char *str[] = {           \
                    "x12+x6+x5+x3+1",     \
                    "x12+x7+x6+x4+1",     \
                    "x11+x8+x4+x+1",      \
                    "x11+x6+x4+x+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
            {
                char *str[] = {           \
                    "x14+x7+x6+x3+x2+x+1",\
                    "x14+x7+x6+x5+x3+x+1",\
                    "x11+x5+x3+x+1",      \
                    "x11+x6+x4+x+1",      \
                    "x12+x6+x4+x+1",      \
                    "x12+x7+x4+x3+1",     \
                    "x11+x6+x5+x+1",      \
                    "x11+x7+x6+x4+1",     \
                    "x11+x7+x6+x5+1",     \
                    "x11+x8+x4+x+1"};
                return str[drv_poly];
            }
        case DRV_FTM_SRAM_TBL_OAM_HASH_KEY:
            {
                char *str[] = {           \
                    "x10+x4+x3+x+1",      \
                    "x10+x5+x2+x+1"};
                return str[drv_poly];
            }
        default:
            return "";
    }

    return "";
}


int32
drv_at_ftm_show_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type)
{
    uint32 drv_poly[DRV_FTM_POLY_TYPE_MAX] = {0};
    uint32 drv_poly1 = 0;
    uint8  poly_num = 0;
    uint8  num = 0;

    _drv_at_ftm_get_hash_poly(lchip, mem_id, sram_type, &drv_poly1);

    DRV_FTM_DBG_OUT("%-20s:  %d\n", "mem_id", mem_id);
    DRV_FTM_DBG_OUT("%-20s:  %s\n", "current-poly", _drv_at_ftm_get_hash_poly_str(lchip, sram_type, drv_poly1));

    _drv_at_ftm_get_hash_drv_poly_cap(lchip, sram_type, mem_id, &poly_num, drv_poly);
    DRV_FTM_DBG_OUT("%-20s:  ", "poly-capability");
    for (num = 0; num < poly_num; num++)
    {
        DRV_FTM_DBG_OUT("%-20s", _drv_at_ftm_get_hash_poly_str(lchip, sram_type, drv_poly[num]));
        if (num && (0 == num % 4))
        {
            DRV_FTM_DBG_OUT("\n%20s", "");
        }
    }
    DRV_FTM_DBG_OUT("\n");
    return DRV_E_NONE;
}


static int32
_drv_at_get_memory_size(uint8 lchip, uint32 mem_id, uint32*p_mem_size)
{
    uint32 sram_type = 0;
    uint32 couple_mode = 0;
    uint8  per_entry_bytes = 0;
    uint32 sram_tbl_a[200] = {0};
    uint8  share_tbl_num  = 0;
    uint8  per_tbl_entry_num = 0;

    DRV_PTR_VALID_CHECK(p_mem_size);

    if (mem_id <= DRV_FTM_SRAM_MAX)
    {
        sram_type = _drv_at_ftm_memid_2_table(lchip, mem_id);
        if (MaxTblId_t == sram_type || DRV_FTM_SRAM_TBL_MAX == sram_type)
        {
            return DRV_E_NONE;
        }
        couple_mode = DRV_FTM_TBL_COUPLE_MODE(sram_type);
        if (DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == sram_type || DRV_FTM_SRAM_TBL_LPM_LKP_KEY1 == sram_type)
        {
            per_entry_bytes = DRV_BYTES_PER_ENTRY;
            *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
        }
        else
        {
            _drv_at_ftm_get_sram_tbl_id(lchip, sram_type, sram_tbl_a, &share_tbl_num, &per_tbl_entry_num);
            per_entry_bytes = DYNAMIC_TABLE_UNIT_SIZE(lchip, sram_tbl_a[0]);
            if (DRV_FTM_TBL_INFO(sram_type).sram_num)
            {
                *p_mem_size = (TABLE_MAX_INDEX(lchip, sram_tbl_a[0]) * per_entry_bytes / DRV_FTM_TBL_INFO(sram_type).sram_num);
            }
        }
    }
    else if (mem_id <= DRV_FTM_TCAM_AD3)
    {
        per_entry_bytes = 16;
        *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
    }
    else if (mem_id <= DRV_FTM_TCAM_AD27)
    {
        per_entry_bytes = 18;
        *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
    }
    else if (mem_id <= DRV_FTM_TCAM_AD39)
    {
        per_entry_bytes = 20;
        *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
    }
    else if(mem_id <= DRV_FTM_TCAM_ADM)
    {
        per_entry_bytes = 12;
        *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
    }
    else if(mem_id <= DRV_FTM_LPM_TCAM_ADM)
    {
        per_entry_bytes = DRV_LPM_KEY_BYTES_PER_ENTRY;
        *p_mem_size = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) * per_entry_bytes << couple_mode;
    }

    return DRV_E_NONE;
}

static int32
_drv_at_ftm_table_id_2_mem_id(uint8 lchip, uint32 tbl_id, uint32 tbl_idx, uint32* p_mem_id, uint32* p_offset)
{
    uint32* mem_bmp = NULL;
    uint8  mem_idx;

    DRV_INIT_CHECK(lchip);
    DRV_PTR_VALID_CHECK(p_mem_id);
    DRV_PTR_VALID_CHECK(p_offset);

    if(!TABLE_EXT_INFO_PTR(lchip,tbl_id) || (TABLE_EXT_TYPE(lchip, tbl_id) == 1))
    {
        return DRV_E_INVAILD_TYPE;
    }
    if(TABLE_EXT_INFO_TYPE(lchip,tbl_id) == EXT_INFO_TYPE_DYNAMIC)
    {
        mem_bmp = DYNAMIC_BITMAP(lchip,tbl_id);
        for(mem_idx=0; mem_idx < DRV_FTM_SRAM_MAX; mem_idx++)
        {
            if(!DRV_BMP_ISSET(mem_bmp, mem_idx))
            {
                continue;
            }

            if((DYNAMIC_START_INDEX(lchip,tbl_id, mem_idx) <= tbl_idx) && (tbl_idx <= DYNAMIC_END_INDEX(lchip, tbl_id, mem_idx)))
            {
                *p_mem_id = mem_idx;
                if (DYNAMIC_ACCESS_MODE(lchip, tbl_id) != DYNAMIC_DEFAULT)
                {
                    *p_offset = (tbl_idx - DYNAMIC_START_INDEX(lchip, tbl_id, mem_idx))*DRV_BYTES_PER_ENTRY;
                }
                else
                {
                    *p_offset = (tbl_idx - DYNAMIC_START_INDEX(lchip, tbl_id, mem_idx))*TABLE_ENTRY_SIZE(lchip, tbl_id);
                }
                return DRV_E_NONE;
            }
        }
    }
    else
    {
        uint32 mem_id_max = 0;
        uint32 mem_id_base = 0;
        switch(TABLE_EXT_INFO_TYPE(lchip,tbl_id))
        {
            case EXT_INFO_TYPE_TCAM:
                if (TCAM_MODULE_LPM == TCAM_KEY_MODULE(lchip, tbl_id))
                {
                    mem_id_max = DRV_CONST(DRV_MAX_LPM_TCAM_NUM);
                    mem_id_base = DRV_FTM_LPM_TCAM_KEY0;
                }
                else
                {
                    mem_id_max = DRV_CONST(DRV_MAX_NOR_TCAM_NUM);
                    mem_id_base = DRV_FTM_TCAM_KEY0;
                }
                break;
            case EXT_INFO_TYPE_TCAM_AD:
                if (TCAM_MODULE_LPM == TCAM_KEY_MODULE(lchip, tbl_id))
                {
                    mem_id_max = DRV_CONST(DRV_MAX_LPM_TCAM_NUM);
                    mem_id_base = DRV_FTM_LPM_TCAM_AD0;
                }
                else
                {
                    mem_id_max = DRV_CONST(DRV_MAX_NOR_TCAM_NUM);
                    mem_id_base = DRV_FTM_TCAM_AD0;
                }
                break;
            default:
               //- DRV_FTM_DBG_OUT("Invalid table id:%d,line:%d\n",tbl_id,__LINE__);
                return DRV_E_INVAILD_TYPE;
        }

        for(mem_idx=0; mem_idx < mem_id_max; mem_idx++)
        {
            if(!DRV_BMP_ISSET(TCAM_BITMAP(lchip,tbl_id), mem_idx))
            {
                continue;
            }

            if((TCAM_START_INDEX(lchip,tbl_id, mem_idx) <= tbl_idx) && (tbl_idx <= TCAM_END_INDEX(lchip,tbl_id, mem_idx)))
            {
                *p_mem_id = mem_idx + mem_id_base;
                *p_offset = (tbl_idx-TCAM_START_INDEX(lchip, tbl_id, mem_idx))*TABLE_ENTRY_SIZE(lchip,tbl_id);
                return DRV_E_NONE;
            }
        }
    }

   //- DRV_FTM_DBG_OUT("Invalid table id, line:%d\n",__LINE__);
    return DRV_E_INVAILD_TYPE;
}

static int32
_drv_at_ftm_get_mem_type(uint8 lchip, drv_ftm_mem_info_t* p_mem_info)
{
   uint16 mem_id = 0;
   uint8 detail_type = 0;
   uint8 mem_type = 0;

   mem_id = p_mem_info->mem_id;
   if (mem_id >= DRV_FTM_MAX_ID)
   {
       return 0;
   }

   mem_type = DRV_MEM_INFO(lchip, mem_id).type;
   detail_type = DRV_MEM_INFO(lchip, mem_id).sub_type;
   p_mem_info->mem_sub_id = DRV_MEM_INFO(lchip, mem_id).sub_id;

   if (p_mem_info->info_type == DRV_FTM_MEM_INFO_MEM_TYPE_DETAIL)
   {
       p_mem_info->mem_type = detail_type;
   }
   else
   {
       p_mem_info->mem_type = mem_type;
   }

   return 0;
}

static int32
_drv_at_ftm_get_mem_tbl_index(uint8 lchip, drv_ftm_mem_info_t* p_mem_info)
{
   uint32 tbl_id = 0;
   uint32 index = 0;
   uint32 mem_id = 0;

   mem_id = p_mem_info->mem_id;

   tbl_id = DsFibHost0MacHashKey_t;

   if (!DRV_BMP_ISSET(DYNAMIC_BITMAP(lchip, tbl_id), mem_id))
   {
       return DRV_E_INVAILD_TYPE;
   }

   index = DYNAMIC_START_INDEX(lchip, tbl_id, mem_id) + (p_mem_info->mem_offset)/TABLE_ENTRY_SIZE(lchip, tbl_id);

   if (index >  DYNAMIC_END_INDEX(lchip, tbl_id, mem_id))
   {
       return DRV_E_INVAILD_TYPE;
   }


   p_mem_info->table_id = tbl_id;
   p_mem_info->index = index;


   return 0;
}

static int32
_drv_at_ftm_get_tcam_memory_info(uint8 lchip,
                                  uint32 mem_id,
                                  uint32* p_mem_addr,
                                  uint32* p_entry_num,
                                  uint32* p_entry_size,
                                  void* tcam_info)
{
    uint8  burst_op = 0;
    uint32 entry_num = 0;
    uint32 tcam_mem_table_id = 0;
    drv_ftm_tcam_info_t* p_tcam_info = tcam_info;
#if (SDK_WORK_PLATFORM == 1)
#define TABLE_HW_ADDR(lchip, tbl_id)    TABLE_INFO(lchip, tbl_id).addrs[1]
#else
#define TABLE_HW_ADDR(lchip, tbl_id)    TABLE_INFO(lchip, tbl_id).addrs[0]
#endif
#define TABLE_SDB_ADDR(lchip, tbl_id)    DRV_SDB_ADDR_BASE(tbl_id)

    tcam_mem_table_id = DRV_TCAM_MAP(lchip, DRV_MEM_INFO(lchip, mem_id).tcam_map_id);
    //-burst_op = !(TABLE_OP_TYPE(lchip, tcam_mem_table_id)&Op_DisBurst) && p_drv_master[lchip]->burst_en;
    *p_mem_addr = DRV_FTM_MEM_HW_DATA_BASE(mem_id) + burst_op;
    if (DRV_FTM_TCAM_KEY2 <= mem_id && mem_id <= DRV_FTM_TCAM_KEY39)
    {
        entry_num = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id) >> 1;
    }
    else
    {
        entry_num = DRV_FTM_MEM_MAX_ENTRY_NUM(mem_id);
    }
    *p_entry_size = TABLE_ENTRY_SIZE(lchip, tcam_mem_table_id);
    if (p_tcam_info)
    {
        p_tcam_info->tcam_mem_id = tcam_mem_table_id;
        p_tcam_info->sw_addr = (uintptr)TABLE_SDB_ADDR(lchip, tcam_mem_table_id) + DRV_FTM_MEM_HW_DATA_BASE(mem_id) - DRV_FTM_MEM_HW_DATA_BASE(mem_id-DRV_MEM_INFO(lchip, mem_id).sub_id);
        p_tcam_info->entry_offset = TABLE_ENTRY_OFFSET(lchip, tcam_mem_table_id);
    }
    *p_entry_num = entry_num;
    /*
    DRV_DBG_INFO("ftm_get_tcam_memory_info: hw_base:0x%x - sw_base:%p - tcam_map_id:%u - tcam_mem_table_id:%u - burst_op:%u - mem_sub_id:%u\n",
           DRV_FTM_MEM_HW_DATA_BASE(mem_id), (uint8*)TABLE_SDB_ADDR(lchip, tcam_mem_table_id), DRV_MEM_INFO(lchip, mem_id).tcam_map_id, tcam_mem_table_id, burst_op, DRV_MEM_INFO(lchip, mem_id).sub_id);
    */
    return DRV_E_NONE;
}

static int32
_drv_at_ftm_get_mem_info(uint8 lchip, drv_ftm_mem_info_t* p_mem_info)
{
    DRV_PTR_VALID_CHECK(p_mem_info);

    switch(p_mem_info->info_type)
    {
    case DRV_FTM_MEM_INFO_MEM_TYPE:
    case DRV_FTM_MEM_INFO_MEM_TYPE_DETAIL:
        _drv_at_ftm_get_mem_type(lchip, p_mem_info);
        break;

    case DRV_FTM_MEM_INFO_TBL_INDEX:
        _drv_at_ftm_get_mem_tbl_index(lchip, p_mem_info);
        break;

    case DRV_FTM_MEM_INFO_ENTRY_ENUM:
        {
            p_mem_info->entry_num = DRV_FTM_TBL_MEM_ENTRY_NUM(0, p_mem_info->mem_id);
        }
        break;

    default:
        break;
    }

    return 0;
}

static int32
_drv_at_ftm_get_flow_stats_table_id(uint8 lchip, uint8 ram_idx, uint32* table_id)
{
    uint32 stats_table_id[] = {
        DsStatsEgressACL0_t,
        DsStatsEgressACL1_t,
        DsStatsEgressACL2_t,
        DsStatsEgressACL3_t,
        DsStatsEgressACL4_t,
        DsStatsEgressACL5_t,
        DsStatsEgressACL6_t,
        DsStatsEgressACL7_t,
        DsStatsEgressACL8_t,
        DsStatsEgressACL9_t,
        DsStatsEgressACL10_t,
        DsStatsEgressACL11_t,
        DsStatsIngressACL0_t,
        DsStatsIngressACL1_t,
        DsStatsIngressACL2_t,
        DsStatsIngressACL3_t,
        DsStatsIngressACL4_t,
        DsStatsIngressACL5_t,
        DsStatsIngressACL6_t,
        DsStatsIngressACL7_t,
        DsStatsIngressACL8_t,
        DsStatsIngressACL9_t,
        DsStatsIngressACL10_t,
        DsStatsIngressACL11_t,
        DsStatsIngressACL12_t,
        DsStatsIngressACL13_t,
        DsStatsIngressACL14_t,
        DsStatsIngressACL15_t,
        DsStatsIngressACL16_t,
        DsStatsIngressACL17_t,
        DsStatsIngressACL18_t,
        DsStatsIngressACL19_t,
        DsStatsIngressACL20_t,
        DsStatsIngressACL21_t,
        DsStatsIngressACL22_t,
        DsStatsIngressACL23_t,

        DsStats0_t,
        DsStats1_t,
        DsStats2_t,
        DsStats3_t,
        DsStats4_t,
        DsStats5_t,
        DsStats6_t,
        DsStats7_t,
        DsStats8_t,
        DsStats9_t,
        DsStats10_t,
        DsStats11_t,
        DsStats12_t,
        DsStats13_t,
        DsStats14_t,
        DsStats15_t,

        DsStatsQueueUc_t,
        DsStatsQueueMc_t,
        DsStatsDmaUc_t,
        DsStatsDmaMc_t,
        DsStatsPortTcUc_t,
        DsStatsPortTcMc_t
    };
    if(ram_idx >= (sizeof(stats_table_id) / sizeof(uint32)))
    {
        return DRV_E_INVALID_INDEX;
    }

    *table_id = stats_table_id[ram_idx];
    return DRV_E_NONE;
}

extern int32 drv_at_ftm_get_ram_with_chip_op(uint8 lchip, uint8 ram_id);
static drv_mchip_ftm_t drv_ftm_api =
{
    _drv_at_ftm_set_hash_poly,
    _drv_at_ftm_get_hash_poly,
    _drv_at_ftm_lookup_ctl_init,
    _drv_at_ftm_mem_alloc,
    _drv_at_ftm_mem_free,
    _drv_at_ftm_get_info_detail,
    _drv_at_ftm_get_sram_type,
    _drv_at_ftm_get_mem_info,
    _drv_at_ftm_table_id_2_mem_id,
    _drv_at_get_memory_size,
    _drv_at_ftm_get_cam_by_tbl_id,
    NULL, /*ftm_set_misc_config*/
    NULL, /*ftm_adjust_flow_tcam*/
    NULL, /*ftm_adjust_mac_table*/
    NULL, /*ftm_reset_tcam_table*/
    NULL, /*ftm_set_dynamic_ram_couple_mode*/
    _drv_at_get_dynamic_ram_couple_mode,
    _drv_at_ftm_get_tcam_tbl_info_detail,
    _drv_at_ftm_get_tcam_memory_info,
    _drv_at_ftm_memid_2_table,
    NULL,
    _drv_at_ftm_get_flow_stats_table_id,
    _drv_at_ftm_sram_get_sdb_en,
    drv_at_ftm_get_ram_with_chip_op,
    NULL,
    NULL,
    drv_at_ftm_mapping_drv_hash_poly_type,
    drv_at_ftm_get_current_hash_poly_type,
    drv_at_ftm_get_hash_poly_cap,
    drv_at_ftm_show_hash_poly,
    _drv_at_ftm_get_sram_tbl_id
};


int32
drv_at_ftm_api_init(uint8 lchip)
{
    p_drv_master[lchip]->mchip_api.p_mchip_ftm  = &drv_ftm_api;

    return 0;
}

int32
drv_usw_ftm_map_tcam_index(uint8 lchip,
                       uint32 tbl_id,
                       uint32 old_index,
                       uint32* new_index)
{
    *new_index = old_index;
    return 0;
}

int32  drv_at_ftm_get_ram_with_chip_op(uint8 lchip, uint8 ram_id)
{
    uint32 bitmap[2] = {0};
    if (ram_id > DRV_FTM_SRAM_MAX)
    {
        return DRV_E_NONE;/*support*/
    }

    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_MAC_HASH_KEY)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_LM)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MEP)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MA)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MA_NAME)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_IPFIX_AD)[0];
    bitmap[0] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_APS)[0];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_MAC_HASH_KEY)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_LM)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MEP)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MA)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_MA_NAME)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_IPFIX_AD)[1];
    bitmap[1] |= DRV_FTM_TBL_MEM_BITMAP(DRV_FTM_SRAM_TBL_OAM_APS)[1];

    if (DRV_BMP_ISSET(bitmap, ram_id))
    {
        return DRV_E_INVALID_MEM;
    }
    else
    {
        return DRV_E_NONE;/*support*/
    }

}
#endif

